FCCM 2012: Program

Sunday April 29, 2012
1:30PM   
Sunday Workshop (HTML)  (PDF) 
6:00PM   
FCCM Opening Reception in the Yorkville Room 



Monday April 30, 2012
8:00AM   
Registration opens



8:30AM   
Opening remarks



8:40AM    Session 1: Architecture



   Chair: Miriam Lesser, Northeastern University, USA



8:40AM    A low-overhead profiling and visualization framework for Hybrid Transactional Memory
Oriol Arcas1,  Philipp Kirchhofer2,  Nehir Sonmez1,  Martin Schindewolf2,  Osman S. Unsal1,  Wolfgang Karl2,  Adrian Cristal1
1Barcelona Supercomputing Center, 2Karlsruhe Institute of Technology



9:00AM    Towards a Universal FPGA Matrix-Vector Multiplication Architecture
John Davis1,  Srinidhi Kestur2,  Eric Chung1
1Microsoft, 2The Pennsylvania State University



9:20AM    Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
Jongsok Choi1,  Kevin Nam1,  Andrew Canis1,  Jason Anderson1,  Stephen Brown1,  Tomasz Czajkowski2
1University of Toronto, 2Altera Corporation



9:40AM    Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers
Manish Kumar Jaiswal and Ray C.C. Cheung
Department of Electronic Engineering, City University of Hong Kong, Hong Kong.



9:45AM    Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA
Eduardo Gudis,  Gooitzen van der Wal,  Sujit Kuthirummal,  Sek Chai
SRI International



9:50AM    A Mixed Precision Methodology for Mathematical Optimisation
Gary Chun Tak Chow1,  Wayne Luk1,  Philip H.W. Leong2
1Imperial College London, 2University of Sydney



9:55AM   
Poster Session 1

1. Area-Efficient Architectures for Large Integer and Quadruple
Precision Floating Point Multipliers (S1)
Manish Kumar Jaiswal and Ray C.C. Cheung

2. Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA (S1)
Eduardo Gudis,  Gooitzen van der Wal,  Sujit Kuthirummal,  Sek Chai

3. A Mixed Precision Methodology for Mathematical Optimisation (S1)
Gary Chun Tak Chow1,  Wayne Luk,  Philip H.W. Leong

4. Enabling Shared-Memory Programming Models on FPGAs with Coherent Caches
Vincent Mirian and Paul Chow

5. EBRAM - Extending BlockRAMs in FPGAs to Support Caches and Hash
Tables in an Efficient Manner.
Andreas Ehilar.

6. VENICE: A Compact Vector Processor for FPGA Applications
Aaron Severance and Guy Lemieux

8. Interface Design for Synthesized Structural Hybrid
Microarchitectural Simulators
Zhuo Ruan and Penry David


11:00AM    Session 2: Reconfiguration



   Chair: Brad Hutchings, Brigham Young University, USA



11:00AM    Go Ahead: A Partial Reconfiguration Framework for Xilinx FPGAs
Christian Beckhoff1,  Dirk Koch2,  Jim Torresen3
1ReCoBus, 2University of Oslo, 3Universtiy of Oslo



11:20AM    On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library
Christopher Dennl,  Daniel Ziener,  Jürgen Teich
University of Erlangen-Nuremberg



11:40AM    Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing
Juan L Jerez,  George A Constantinides,  Eric C Kerrigan
Imperial college



12:00PM    Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures
Spyros Lyberis,  George Kalokerinos,  Michalis Lygerakis,  Vassilis Papaefstathiou,  Dimitris Tsaliagkos,  Manolis Katevenis,  Dionisios Pnevmatikatos,  Dimitris Nikolopoulos
FORTH-ICS



12:05PM    Fast Multi-Objective Algorithmic-Design Co-Exploration for FPGA-based Accelerators
Kumud Nepal,  Onur Ulusel,  Iris Bahar,  Sherief Reda
Brown University



12:10PM   
Lunch



1:40PM    Session 3: Applications 1



   Chair: Eric Chung, Microsoft Research, USA



1:40PM    FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection using reconfigurable ASIP
Xiaolin Chen,  Andreas Minwegen,  Yahia Hassan,  David Kammler,  Shuai Li,  Torsten Kempf,  Anupam Chattopadhyay,  Gerd Ascheid
Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Aachen, Germany



2:00PM    FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models using Gappa++
Helene Martorell1 and Nachiket Kapre2
1National Polytechnic Institute of Toulouse, 2Imperial College London



2:20PM    FPGA-based Acceleration for Tracking Audio Effects in Movies
Mihalis Psarakis,  Aggelos Pikrakis,  Giannis Dendrinos
University of Piraeus, Greece



2:45PM    ZUMA: An Open FPGA Overlay Architecture
Alex Brant and Guy Lemieux
Dept of ECE, UBC



2:50PM    Efficient Query Processing for Web Search Engine with FPGAs
Jing Yan1,  Zhan-Xiang Zhao1,  Ning-Yi Xu1,  Xi Jin2,  Lin-Tao Zhang1,  Feng-Hsiung Hsu1
1Microsoft Research Asia, 2University of Science and Technology of China



2:55PM   
Poster Session 2

1. Formic: Cost-efficient and Scalable Prototyping of Manycore
Architectures (S2)
Spyros Lyberis,  George Kalokerinos,  Michalis Lygerakis,  Vassilis
Papaefstathiou,  Dimitris Tsaliagkos,  Manolis Katevenis,  Dionisios
Pnevmatikatos,  Dimitris Nikolopoulos

2. Fast Multi-Objective Algorithmic-Design Co-Exploration for
FPGA-based Accelerators (S2)
Kumud Nepal,  Onur Ulusel,  Iris Bahar,  Sherief Reda

3. ZUMA: An Open FPGA Overlay Architecture (S3)
Alex Brant and Guy Lemieux

4. Efficient Query Processing for Web Search Engine with FPGAs (S3)
Jing Yan,  Zhan-Xiang Zhao,  Ning-Yi Xu,  Xi Jin,  Lin-Tao Zhang,
Feng-Hsiung Hsu

5. Implementing Mutex Variables in an FPGA Cache
Vincent Mirian and Paul Chow

6. Large-scale Router Virtualization on FPGA using Feature-based Clustering
Thilan Ganegedara, Hoang Le and Viktor Prasanna

7. Shared Instruction-set Extensions for Soft Multi-core Systems
Erin Johnston and Peter Hallschmid

8. Variable-length radix-8/4/2 FFT for OFDM
Jungmin Park, Phillip H. Jones and Akhilesh Tyagi


4:00PM    Session 4: Power and Measurement



   Chair: Jason Anderson, University of Toronto, Canada



4:00PM    Power Management Strategies for Serial RapidIO Endpoints in FPGAs
Moritz Schmid,  Frank Hannig,  Jürgen Teich
University Erlangen-Nuremberg



4:20PM    Online Measurement of Timing in Circuits: for Health Monitoring & Dynamic Voltage and Frequency Scaling
Joshua Levine,  Edward Stott,  George A. Constantinides,  Peter Y.K. Cheung
Imperial College London



4:45PM    An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems
Yamuna Rajasekhar,  Rahul Sharma,  Ron Sass
University of North Carolina at Charlotte



4:50PM    Remote Execution in Distributed Memory MPSoC
Remi Busseuil,  Luciano Ost,  Rafael Garibotti,  Gilles Sassatelli,  Michel Robert
LIRMM



6:30PM   
Demo Night



Tuesday 1 May 2012
8:00AM   
Registration opens



8:40AM    Session 5: Applications 2



   Chair: Mike Butts, Nvidia, USA



8:40AM    A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs
Isaac Liu1,  Matthew Viele2,  Guoqiang Wang3,  Edward Lee1,  Hugo Andrade3
1UC Berkeley, 2Drivven, Inc., 3NI



9:00AM    Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation
Simon Moore,  Paul Fox,  Steven Marsh,  A. Theodore Markettos,  Alan Mujumdar
University of Cambridge



9:20AM    Emulating Mammalian Vision on Reconfigurable Hardware
Srinidhi Kestur1,  Mi Sun Park1,  Jagdish Sabarad1,  Dharav Dantara1,  Vijaykrishnan Narayanan1,  Yang Chen2,  Deepak Khosla2
1Pennsylvania State University, 2HRL Laboratories



9:40AM    Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs
Gabriel Nazar and Luigi Carro
Universidade Federal do Rio Grande do Sul



9:45AM    Custom Precision Based Architectures for Accelerating Parallel Tempering MCMC in FPGAs
Grigorios Mingas and Christos-Savvas Bouganis
Imperial College London



9:50AM    Exploiting Memory-Level Parallelism in Reconfigurable Accelerators
Shaoyi Cheng1,  Mingjie Lin2,  Hao Jun Liu1,  Simon Scott1,  John Wawrzynek1
1Department of Electrical Engineering and Computer Science, University of California, Berkeley, 2Department of Electrical Engineering and Computer Science, University of Central Florida



9:55AM   
Poster Session 3

1.  An Extensible and Portable Tool Suite for Managing Multi-Node FPGA
Systems  (S4)
Yamuna Rajasekhar,  Rahul Sharma,  Ron Sass

2. Remote Execution in Distributed Memory MPSoC (S4)
Remi Busseuil,  Luciano Ost,  Rafael Garibotti,  Gilles Sassatelli,
Michel Robert

3. Custom Precision Based Architectures for Accelerating Parallel
Tempering MCMC in FPGAs (S5)
Grigorios Mingas and Christos-Savvas Bouganis

4.  Exploiting Memory-Level Parallelism in Reconfigurable Accelerators (S5)
Shaoyi Cheng1,  Mingjie Lin2,  Hao Jun Liu1,  Simon Scott1,  John Wawrzynek1

5. Implementing Murphi: An Illustration of Accelerating Large State
Space Exploration on an FPGA
Mary Ellen Tie and Miriam Leeser

6. Designing flexible reconfigurable regions to relocate partial bitstreams
Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida,
Morihiro Kuga and Toshinori Sueyoshi

7. Exploiting Modified Placement and Hardwired Resources to Provide
High Reliability in FPGAs  (S5)
Gabriel Nazar and Luigi Carro


11:00AM    Session 6: Bioinfomatics



   Chair: Ron Sass, University of North Carolina, USA



11:00AM    A Hardware Acceleration of Short Read Mapping
Best Paper Award!
Corey Olson1,  Maria Kim2,  Cooper Clauson2,  Boris Kogon2,  Carl Ebeling2,  Scott Hauck2,  Walter Ruzzo3
1Pico Computing, University of Washignton, 2University of Washington, 3University of Washington, Fred Hutchinson Cancer Research Center



11:20AM    Short-Read Mapping by a Systolic Custom FPGA Computation
Thomas B. Preußer,  Oliver Knodel,  Rainer G. Spallek
TU Dresden



11:40AM    FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment Through Pipelined Prefiltering
Atabak Mahram and Martin Herbordt
Boston University



12:00PM    Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator
Wen TANG,  Wendi WANG,  Bo DUAN,  Chunming ZHANG,  Guangming TAN,  Peiheng ZHANG,  Ninghui SUN
High Performance Computer Research Center, Institute of Computing Technology, Chinese Academy of Sciences



12:05PM    Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes
Berkin Akin,  Peter Milder,  Franz Franchetti,  James Hoe
Carnegie Mellon University



12:10PM   
Lunch



1:40AM    Session 7: Compilers and Systems



   Chair: Maya Gokhale, Lawrence Livermore National Lab, USA



1:40PM    Specifying Compiler Strategies for FPGA-based Systems
João Cardoso1,  João Teixeira1,  José Alves1,  Ricardo Nobre2,  Pedro Diniz2,  José Coutinho3,  Wayne Luk3
1Universidade do Porto, 2INESC-ID, 3Imperial College London



2:00PM    Bus-based MPSoC security through communication protection: A latency-efficient alternative
Pascal Cotret1,  Jérémie Crenne2,  Guy Gogniat1,  Jean-Philippe Diguet1
1Laboratoire Lab-STICC, Université de Bretagne-Sud, Lorient (France), 2Laboratoire LIRMM, Université de Montpellier 2, Montpellier (France)



2:20PM    PATS: a Performance Aware Task Scheduler for Runtime Reconfigurable Processors
Lars Bauer,  Artjom Grudnitsky,  Muhammad Shafique,  Jörg Henkel
Karlsruhe Institute of Technology



2:40PM    RIFFA: A reusable integration framework for FPGA accelerators
Matthew Jacobsen,  Ryan Kastner,  Yoav Freund
University of California, San Diego



2:45PM    Groundhog - Serial ATA Host Bus Adapter (HBA) for FPGAs
Louis Woods1 and Ken Eguro2
1ETH Zurich, 2Microsoft



2:50PM   
Poster Session 4

1. Accelerating Millions of Short Reads Mapping on a Heterogeneous
Architecture with FPGA Accelerator (S6)
Wen TANG,  Wendi WANG,  Bo DUAN,  Chunming ZHANG,  Guangming TAN,
Peiheng ZHANG,  Ninghui SUN

2, Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform
Algorithm and Implementation for Large Problem Sizes (S6)
Berkin Akin,  Peter Milder,  Franz Franchetti,  James Hoe

3. RIFFA: A reusable integration framework for FPGA accelerators (S7)
Matthew Jacobsen,  Ryan Kastner,  Yoav Freund

4.  Groundhog - Serial ATA Host Bus Adapter (HBA) for FPGAs (S7)
Louis Woods1 and Ken Eguro2
1ETH Zurich, 2Microsoft

5. Memory Interface Optimization for the High-Level Synthesis of
Data-Intensive Kernels
Zheming Jinz and Jason Bakos

6. ScalaPipe: A Streaming Application Generator
Joseph Wingbermuehle, Roger Chamberlain and Ron Cytron

7. Cognitive Radio Universal Software Hardware
George Eichinger, Kaushik Chowdhury and Miriam Leeser


4:00PM    Session 8: GPUs and Data Parallelism



   Chair: Greg Steffan, University of Toronto, Canada



4:00PM    Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case
Gabriel Falcao1,  Muhsen Owaida2,  David Novo3,  Madhura Purnaprajna3,  Nikolaos Bellas2,  Christos D. Antonopoulos2,  Georgios Karakonstantis3,  Andreas Burg3,  Paolo Ienne3
1Department of Electrical and Computer Engineering, University of Coimbra, Portugal, 2Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece, 3Ecole Polytechnique Fédéral de Lausanne (EPFL), Switzerland



4:20PM    Accelerating a random forest classifier: multi-core, GP-GPU, or FPGA?
Brian Van Essen,  Chris Macaraeg,  Ryan Prenger,  Maya Gokhale
Lawrence Livermore National Laboratory



4:40PM   
Wrap up and Best Paper Awards



5:00PM   
Close