High-Performance dense stereo algorithm is a critical component of computer vision systems for augmented reality, video analytics, and visual navigation. In this paper, we propose a low-power, high performance FPGA implementation suitable for embedded real-time platforms. The design is scalable for higher resolution images and frame rates, supporting different camera and application requirements. We achieve that by creating a highly parallel implementation of computation cores with a very efficient memory access to the image data. Using a prototype board, we demonstrate real-time stereoscopy with GigE Vision cameras at 30 frames per second. We show that this FPGA design is 10 times more power efficient, and much more scalable and lower latency, in comparison with previous software based implementation on a GPU.