Abstract—The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is typically a long and error-prone process. In addition to developing the required functions, developers need to be deeply involved on code transformations and optimizations to achieve the required performance. This paper describes the use of a novel aspect-oriented hardware/software design-flow for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language devoted to high-level specifications of compilation and application mapping strategies, i.e., sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition an application between hardware and software components and orchestrate its execution on alternative architectures. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5 and 6.8 over software-only implementations. As the approach described allows developers to maintain a single application source code, it promotes developer productivity as well as code and performance portability.