The high area and power demands of traditional modular redundancy techniques make it very expensive to provide high reliability in FPGAs. Possible scenarios for future technologies also increase desirable features of fault tolerance techniques, such as coping with multiple faults and reducing error latency. On the other hand, current high-end FPGAs present, besides lookup tables and flip-flops, several dedicated components that perform the most commonly required functions, such as addition and multiplication. The amount of such resources, however, is frequently overdimensioned, leaving a significant area unused. In this paper, we propose an approach to use such resources to efficiently provide fault detection capabilities. We further extend the technique with placement constraints to enhance the detection of faults affecting the routing resources, which is a critical demand for such devices. Results are presented considering fault injection experiments performed with traditional benchmark circuits on a real FPGA device.