The reconfigurability of Field Programmable Gate Arrays (FPGAs) makes them an attractive platform for accelerating algorithms. Accelerating a particular algorithm is a challenging task as the large number of possible algorithmic and hardware design parameters lead to different accelerator variant implementations, each with its own metrics such as performance, area, power, and arithmetic accuracy characteristics. To identify the algorithmic and design parameters that optimize the accelerator with respect to certain metrics, we propose techniques for fast design space exploration and techniques for non-linear multi-objective optimization. Our methodology samples a small part of the design space and uses measurements from the sampled implementations to train mathematical models for the different metrics. To automate and improve the model generation process, we propose the use of L1-regularized least squares regression techniques. We then propose to use the trained mathematical models within a non-linear optimization framework to identify the optimal algorithm and design parameters under various objectives and constraints. To demonstrate the effectiveness of our approach, we implement a high-throughput real-time accelerator for image debluring and show that various choices for the accelerator can be made at the algorithmic and hardware design levels. We demonstrate the accuracy (e.g., within 8% for power modeling) of our modeling techniques and their ability to identify the optimal accelerator designs with large speed-ups (340x) in comparison to brute-force enumeration. We also identify the optimal algorithmic and design parameters for the accelerator for a number of scenarios (e.g., minimize power under arithmetic inaccuracy bounds).