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Sunday 1st May
13:30 - 15:30	How could we achieve an Arduino-like Fast Start for FPGAs?
16:00 - 18:00	Future of Heterogeneous Computing: A government perspective
19:00 - 21:00	FCCM 2016 Opening Reception
Monday 2nd May - Day 1
07:45 - 08:40	Breakfast and Registration
08:40 - 09:00	Welcoming Remarks
09:00 - 09:50	Paper Session M1 : Overlays
09:50 - 11:00	Poster Session P1
11:00 - 11:45	Paper Session M2 : Applications 1 (Artificial Neural Networks & Computational Biology)
11:45 - 13:15	Lunch
13:15 - 13:35	Announcements
13:35 - 14:50	Paper Session M3 : CAD, Synthesis, and Compilers 1
14:50 - 16:00	Poster Session P2
16:00 - 17:00	Paper Session M4 : Applications 2 (Data & Operation Scheduling)
17:00 - 18:30	...
18:30 - 21:00	Demo Night
Tuesday 3rd May - Day 2
08:40 - 09:00	Announcements
09:00 - 09:50	Paper Session T1 : Hardware Debug
09:50 - 11:00	Poster Session P3
11:00 - 11:55	Paper Session T2 : CAD, Synthesis, and Compilers 2
11:55 - 13:25	Lunch
13:25 - 14:20	Paper Session T3 : Applications 3 (Computational Physics and Geography)
14:20 - 15:30	Poster Session P4
15:30 - 16:10	Paper Session T4 : Applications 4 (Big Data)
16:10 - 16:30	Best Paper Award and Closing Remarks
Wednesday 4th May & Thursday 5th May
All Day	Designing Xilinx Zynq-based Systems with SDSoC PDF

Demo Night

Each year we have an informal show-and-tell called Demo Night. This year it's Monday evening, May 2, 2015 at 18:30. Paper and poster authors and commercial vendors bring their FCCMs, hardware, gateware, slideware, software, tools, chips, and set up demos. Attendees circulate, enjoy the demos, and engage with the presenters while enjoying the food and drink at this stand-up and learn event. It's always informative for demoers and demoees, great networking, and lots of fun too.

Technical Programme : Papers

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Monday 2nd May
07:45 - 08:40	Breakfast and Registration
08:40 - 09:00	Welcoming Remarks
09:00 - 09:50	Paper Session M1 : Overlays Chair: TBD
09:00 - 09:20	DeCO: A DSP Block Based FPGA Accelerator Overlay With Low Overhead Interconnect Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell and Suhaib A. Fahmy
09:20 - 09:40	High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors Henry Wong, Vaughn Betz and Jonathan Rose
09:40 - 09:45	Best Short Paper 2016 GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator Jan Gray
09:45 - 09:50	Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, and Ryan Kastner
09:50 - 11:00	Poster Session P1
11:00 - 11:45	Paper Session M2 : Applications 1 (Artificial Neural Networks & Computational Biology Chair: TBD
11:00 - 11:20	The SMEM Seeding Algorithm Acceleration for DNA Sequence Alignment Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo and Cody Hao Yu
11:20 - 11:40	fpgaConvNet: A framework for mapping Convolutional Neural Networks on FPGAs Stylianos I. Venieris and Christos-Savvas Bouganis
11:40 - 11:45	Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines using Dropout Jiang Su, David B. Thomas and Peter Y. K. Cheung
11:45 - 11:50	Two-Hit Filter Synthesis for Genomic Database Search Jordan A. Bradshaw, Rasha Karakchi and Jason D. Bakos
11:50- 13:15	Lunch
13:15 - 13:35	Announcements
13:35 - 14:50	Paper Session M3 : CAD, Synthesis, and Compilers 1 Chair: TBD
13:35 - 13:55	Best Paper 2016 KAPow: A System Identification Approach to Online Per-module Power Estimation in FPGA Designs Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y.K. Cheung and George A. Constantinides
13:55 - 14:15	SynADT: Dynamic Data Structures in High Level Synthesis Zeping Xue and David B. Thomas
14:15 - 14:35	Loop Splitting for Efficient Pipelining in High-Level Synthesis Junyi Liu, John Wickerson and George A. Constantinides
14:35 - 14:40	Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure Nachiket Kapre, Que Yanghua, Harnhua Ng and Kirvy Teo
14:40 - 14:45	Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, and Timothy Todman
14:45 - 14:50	Reconfiguration Control Networks for TMR Systems with Module-Based Recovery Dimitris Agiakatsikas, Nguyen T.H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, and Lingkan Gong
14:50 - 16:00	Poster Session P2
16:00 - 17:00	Paper Session M4 : Applications 2 (Data & Operation Scheduling) Chair: TBD
16:00 - 16:20	Parallel Hardware Merge Sorter Wei Song, Dirk Koch, Mikel Luján and Jim Garside
16:20 - 16:40	High-Throughput and Energy-efficient Graph Processing on FPGA Shijie Zhou, Charalampos Chelmis and Viktor Prasanna
19:00 - 21:00	Demo Night
Tuesday 3rd May
08:40 - 09:00	Announcements
09:00 - 09:50	Paper Session T1 : Hardware Debug Chair: TBA
09:00 - 09:20	Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-reconfiguration (COSMIC TRIP) Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim and André Dehon
09:20 - 09:40	Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA Dana How and Sean Atsatt
09:40 - 09:45	AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS Liwei Yang, Swathi Gurumani, Deming Chen and Kyle Rupnow
09:45 - 09:50	Cost Effective Partial Scan for Hardware Emulation Tao Li and Qiang Liu
9:50 - 11:00	Poster Session P3
11:00 - 11:55	Paper Session T2 : CAD, Synthesis, and Compilers 2 Chair: TBA
11:00 - 11:20	A Multi-Ported Memory Compiler Utilizing True Dual-port BRAMs Ameer M.S. Abdelhadi and Guy G.F. Lemieux
11:20 - 11:40	P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers Pavel Benácek, Viktor Puŝ and Hana Kubátová
11:40 - 12:00	Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs Nachiket Kapre
12:00 - 12:05	Parallelizing FPGA Technology Mapping through Partitioning Chuyu Shen, Zili Lin, Ping Fan, Xianglong Meng and Weikang Qian
12:05 - 12:10	Online Bandwidth Reduction Using Dynamic Partial Reconfiguration Seyyed Mahdi Najmabadi, Zhe Wang, Yousef Baroud and Sven Simon
12:10 - 12:15	Energy Efficiency of Fully Pipelining: A Case Study for Matrix Multiplication Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, and André Dehon
12:15 - 13:25	Lunch
13:25 - 14:20	Paper Session T3 : Applications 3 (Computational Physics and Geography) Chair: TBA
13:25 - 13:45	Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware Dajung Lee, Roger Moussalli, Sameh Asaad and Mudhakar Srivatsa
13:45 - 14:05	A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment Tanja Harbaum, Mahmoud Seboui, Matthias Balzer, Jürgen Becker and Marc Weber
14:05 - 14:10	FPGA-Accelerated Particle-Grid Mapping Ahmed Sanaullah, Arash Khoshparvar, and Martin C. Herbordt
14:10 - 15:30	Poster Session P4
15:30 - 16:10	Paper Session T4 : Applications 4 (Big Data) Chair: TBA
15:30 - 15:50	Runtime Parameterizable Regular Expression Operators for Databases Zsolt István, David Sidler and Gustavo Alonso
15:50 - 16:10	Accelerating Equi-Join on a CPU-FPGA Heterogeneous Platform Ren Chen and Viktor Prasanna
16:10 - 16:30	Best Paper Award and Closing Remarks

Technical Programme : Posters

Monday 2nd May
07:45 - 08:40	Breakfast and Registration
08:40 - 09:00	Welcoming Remarks
09:00 - 09:50	Paper Session M1 : Overlays
09:50 - 11:00	Poster Session P1
	GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator Jan Gray
	Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, and Ryan Kastner
	Evaluating Embedded FPGA Accelerators for Deep Learning Applications Gopalakrishna Hegde, Siddhartha , Nachiappan Ramasamy, Vamsi Buddha and Nachiket Kapre
	Communication Optimizations for the 16-core Epiphany Floating-Point Processor Array Siddhartha and Nachiket Kapre
	A LUT-Based Approximate Adder Jorge Echavarria, Andreas Becher, Stefan Wildermann, Jürgen Teich and Daniel Ziener
	Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms Ernst Joachim Houtgast, Vlad-Mihai Sima, Giacomo Marchiori, Koen Bertels and Zaid Al-Ars
	When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei and Peng Wei
	Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal? Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin and Stanislav Sedukhin
	RP-ring: A Heterogeneous multi-FPGA Accelerating Solution for N-body Simulations Tianqi Wang, Xi Jin, Bo Peng, Chuanjun Wang, and Linlin Zheng
11:00 - 11:45	Paper Session M2 : Applications 1 (Artificial Neural Networks & Computational Biology)
11:45 - 13:15	Lunch
13:15 - 13:35	Announcements
13:35 - 14:50	Paper Session M3 : CAD, Synthesis, and Compilers 1
14:50 - 16:00	Poster Session P2
	Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines using Dropout Jiang Su, David B. Thomas and Peter Y. K. Cheung
	Regular Expression Synthesis for BLAST Two-Hit Filtering Jordan A. Bradshaw, Rasha Karakchi and Jason D. Bakos
	Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure Nachiket Kapre, Que Yanghua, Harnhua Ng and Kirvy Teo
	Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, and Timothy Todman
	Reconfiguration Control Networks for TMR Systems with Module-Based Recovery Dimitris Agiakatsikas, Nguyen T.H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, and Lingkan Gong
	Vertex-Centric Distributed Graph Processing on FPGA Nina Engelhardt and Hayden Kwok-Hay So
	High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two William Diehl and Kris Gaj
	Accelerating Apache Spark Big Data Analysis with FPGAs Ehsan Ghasemi and Paul Chow
16:00 - 17:00	Paper Session M4 : Applications 2 (Data & Operation Scheduling)
18:30 - 21:00	Demo Night
Tuesday 3rd May
09:00 - 09:50	Paper Session T1 : Hardware Debug
9:50 - 11:00	Poster Session P3
	AutoSLIDE: Automatic Source-Level Instrumentation and Debugging Liwei Yang, Swathi Gurumani, Deming Chen and Kyle Rupnow
	Cost Effective Partial Scan for Hardware Emulation Tao Li and Qiang Liu
	Initiation Interval Aware Resource Sharing for FPGA DSP Blocks Ronak Bajaj and Suhaib A. Fahmy
	A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi, and Marco Lattuada
	Acceleration of the Pair-HMM algorithm for DNA Variant Calling Gowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-Mei W Hwu and Deming Chen
	An Emperical Analysis of the Fidelility of VPR Area Models Farheen Khan and Andy Ye
	Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC Amine Ait Si Ali, Xiaojun Zhai, Abbes Amira, Faycal Bensaali and Naeem Ramzan
11:00 - 11:55	Paper Session T2 : CAD, Synthesis, and Compilers 2
11:55 - 13:25	Lunch
13:25 - 14:20	Paper Session T3 : Applications 3 (Computational Physics and Geography)
14:20 - 15:30	Poster Session P4
	Parallelizing FPGA Technology Mapping through Partitioning Chuyu Shen, Zili Lin, Ping Fan, Xianglong Meng and Weikang Qian
	Online Bandwidth Reduction Using Dynamic Partial Reconfiguration Seyyed Mahdi Najmabadi, Zhe Wang, Yousef Baroud and Sven Simon
	FPGA-Accelerated Particle-Grid Mapping Ahmed Sanaullah, Arash Khoshparvar, and Martin C. Herbordt
	Finding Space-Time Stream Permutations for Minimum Memory and Latency Thaddeus Koehn and Peter Athanas
	Energy Efficiency of Fully Pipelining: A Case Study for Matrix Multiplication Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, and André Dehon
	Application-Aware Collective Communication on FPGA Clusters (Extended Abstract) Jiayi Sheng, Qingqing Xiong, Chen Yang, and Martin C. Herbordt
	Bridging the Performance-Programmability Gap for FPGAs via OpenCL: A Case Study with OpenDwarfs Konstantinos Krommydas, Ahmed E. Helal, Anshuman Verma and Wu-Chun Feng
	ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling Zhiyuan Yang, Caleb Serafy and Ankur Srivastava
	FPGA-Based Reduction Techniques for Efficient Deep Neural Network Deployment Adam Page and Tinoosh Mohsenin
	CS-based Secured Big Data Processing on FPGA Amey Kulkarni, Ali Jafari, Colin Shea and Tinoosh Mohsenin
	High level synthesis based E-Nose system for gas applications Amine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar, Muhammad Hassan and Amine Bermak
15:30 - 16:10	Paper Session T4 : Applications 4 (Big Data)
16:10 - 16:30	Best Paper Award and Closing Remarks