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Wednesday Workshops

[08:00 - 12:00] - Wednesday May 2

Title: FPGA-based Accelerated Cloud Computing with AWS EC2 F1 and SDAccel (Xilinx)

Presenter: Parimal Patel, XUP Senior Systems Engineer

Abstract

The increasing computational requirements of next-generation Cloud and High-Performance Computing (HPC) applications are pushing the adoption of accelerated computing based on heterogeneous architectures into mainstream, as traditional CPU technology is unable to keep pace. FPGA accelerators complement CPU-based architectures and deliver significant performance and power efficiency improvements. In this regard, Xilinx FPGAs are now available on the Amazon Elastic Compute Cloud (EC2) F1 instances, which are designed to accelerate data center workloads, including machine learning inference, data analytics, video processing, and genomics. These are available in two different sizes that include up to eight Virtex UltraScale+ VU9P FPGAs. Furthermore, Amazon Web Services offers the SDAccel Development Environment for cloud acceleration, enabling the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto the heterogeneous CPU-FPGA system. The high performance and high-level of scalability offered by F1 instances, paired with the power and ease of use of Xilinx SDAccel, is very appealing for the development of high high-performance FPGA-based accelerated solutions, and will be the focus of this tutorial.

Topics to be covered:

Introduction to FPGA-based acceleration, development framework, platform, and use cases Hands-on-experience:

• How to connect to an AWS EC2 F1 instance
• Use AWS F1 instance to accelerate complex workloads
• Developing and optimizing AWS F1 applications with SDAccel
• Optimizing host and FPGA code
• Integrating RTL-based IP into SDAccel-based code

Attendees will use their laptops to connect to the WiFi network and use AWS and work with SDAccel.
There is a charge to attend the workshop. The charge will be $50 which will cover the meal cost during the workshop and the attendees will receive a credit voucher to continue their work on AWS EC2.

[13:00 - 17:00] - Wednesday May 2

Title: High-Level Synthesis with Intel FPGAs (Intel)

Abstract

The Intel HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. In this workshop, we will discuss the features and benefits of using the Intel HLS Compiler. Through hands-on exercises, you'll learn to create an FPGA component in software, co-simulate that component using an RTL simulator with a software testbench, and integrate that component within an FPGA design. Lastly you will learn how to optimize the component execution and memory usage by analyzing compiler generated reports.

Skills Required

• Basic understanding of the C programming language
• Basic understanding of FPGAs and the Intel Quartus Development Environment