| Monday, April 18, 2005 |
| Paper Session 1 : Applications I
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Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs
Zachary K. Baker, Viktor K. Prasanna
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A Novel 2D Filter Design Methodology for Heterogeneous Devices
Christos-Savvas Bouganis, George A. Constantinides, Peter Y.K. Cheung
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Prototyping Architectural Support for Program Rollback Using FPGAs
Radu Teodorescu, Josep Torrellas
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| Poster Session 1 |
| Paper Session 2 : Architecture
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Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
Zion Kwok, Steven J.E. Wilton
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Handling Different Computational Granularity by a Reconfigurable IC featuring Embedded FPGAa and a Network-on-Chip
Francesco Lertora, Michele Borgatti
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| Paper Session 3 : Tools I
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A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Roman Lysecky, Frank Vahid, Sheldon X.-D. Tan
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Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller
Lesley Shannon, Paul Chow
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Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures
Pedro C. Diniz
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| Poster Session 2 |
| Paper Session 4 : Graphics
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FPGA Particle Graphics Hardware
John S. Beeckler, Warren J. Gross
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Reconfigurable Designs for Radiosity
Paul Baker, Tim Todman, Henry Styles, Wayne Luk
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| Tuesday, April 19, 2005 |
| Paper Session 5 : Applications II
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Hardware Factorization Based on Elliptic Curve Method
Martin Simka, Jan Pelzl, Thorsten Kleinjung, Milos Drutarovsky, Viktor Fischer, Christof Paar
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Metropolitan Road Traffic Simulation on FPGAs
Justin L. Tripp, Henning S. Mortveit, Anders A. Hansson, Maya Gokhale
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Time Domain Numerical Simulation for Transient Wave Equations on Reconfigurable Coprocessor Platform
Chuan He, Wei Zhao, Mi Lu
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| Poster Session 3 |
| Paper Session 6 : Run Time
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COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors
Jingzhao Ou, Viktor K. Prasanna
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An Execution Environment for Reconfigurable Computing
W. Fu, K. Compton
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| Paper Session 7 : Arithmetic
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Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
Bryan Catanzaro, Brent Nelson
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An Analysis of the Double-Precision Floating-Point FFT on FPGAs
K. Scott Hemmert, Keith Underwood
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A Comparision of Floating Point and Logarithmic Number Systems for FPGAs
Michael Haselman, Michael Beauchamp, Aaron Wood, Scott Hauck, Keith Underwood, K. Scott Hemmert
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| Poster Session 4 |
| Paper Session 8 : Device Architecture
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Terrestrial-Based Radiation: A Cautionary Tale
Heather Quinn, Paul Graham
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Automating the Layout of Reconfigurable Subsystems using Circuit Generators
Shawn Phillips, Scott Hauck
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| Wednesday, April 20, 2005 |
| Paper Session 9 : Networking
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Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network
Young H. Cho, William H. Mangione-Smith
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A Framework For Rule Processing in Reconfigurable Network Systems
Michael E. Attig, John W. Lockwood
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A Signature Match Processor Architecture for Network Intrusion Detection
Janardham Singaraju, Long Bu, John A. Chandy
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| Poster Session 3 |
| Paper Session 10 : Tools II
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Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation
Jose Gabriel F. Coutinho, Jun Jiang, Wayne Luk
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Modeling and FPGA Implementation of Applications using Parameterized Process Networks with Non-Static Parameters
Hristo Nikolov, Todor Stefanov, Ed Deprettere
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