| Monday, April 30, 2001 |
| Paper Session 1 : DSP
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Parallelization of MATLAB Applications for a multi-FPGA System
A. Nayak et. al.
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Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
S-W. Ong, et. al.
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Parameterized Module Generator for an FPGA-Based Electronic Cochlea
M.P. Leong, C.T. Jin and P.H.W. Leong
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| Poster Session 1 |
| Paper Session 2 : Tools
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Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units
J. Cardoso
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Instrumenting Bitstreams for Debugging FPGA Circuits
P. Graham, B. Nelson and B. Hutchings
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| Paper Session 3 : Arithmetic
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The Multiple Wordlength Paradigm
G. Constantinides, P.Y.K. Cheung, W. Luk
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FPGA Implementation of Pipelined On-line Scheme for 3-D Vector Normalization
Z. Huang and M. Ercegovac
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A Reconfigurable Co processor for Variable Long Precision Arithmetic Using Indian Algorithms
R. Parthasarathy et. al.
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| Poster Session 2 |
| Paper Session 4 : JBits
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An efficient content-addressable memory implementation using
Philip B James-Roxby
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Lava and JBits: From HDL to Bitstream in Seconds
S. Singh and P. James-Roxby
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| Tuesday, May 1, 2001 |
| Paper Session 5 : Architecture I
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| Poster Session 3 |
| Paper Session 6 : Tools for Run Time Reconfiguration
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Architecture and Application of PLATO, A Reconfigurable Active Network Platform
A. Dollas et. al.
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Totem: Custom Reconfigurable Array Generation
K. Compton and S. Hauck
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A Cellular Automata System with FPGA
T. Kobori et. al.
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| Paper Session 7 : Fault Tolerance
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A Fault-Tolerance Scheme for a MIN-based Multi-Sensor System
M. Alderighi et. al.
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Column-Based Precompiled Configuration Techniques for FPGA Fault Tolerance
W-J. Huang and E. McCluskey
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| Poster Session 4 |
| Paper Session 8 : Applications I
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Acceleration of a 2D-FFT on an Adaptable Computing Cluster
K. Underwood, R. Sass and W. Ligon
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Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA
A. Benkrid, D. Crookes, K. Benkrid
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| Wednesday, May 2, 2001 |
| Paper Session 9 : Image Processing
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An Application-Specific Compiler for High-Speed Binary Image Morphology
S. Hemmert and B. Hutchings
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One-step compilation of image processing applications to FPGAs
W. Bohm et. al.
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High Level Programming for FPGA Based Image and Video Processing using Hardware Skeletons
K. Benkrid
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| Poster Session 3 |
| Paper Session 10 : Applications II
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Fast Regular Expression Matching using FPGAs
R. Sidhu and V. Prasanna
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A Configurable Hardware/Software Approach to SAT Solving
J. de Sousa, J. da Silva, and M. Abramovici
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