| Wednesday, April 17, 2000 |
| Paper Session 1 : Architecture
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Design of a VLIW Compute Accelerator on the Transmogrifier-2
L. Zhang, Q. Wang, and D. Lewis
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A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
M. Boyd and T. Lurrabee
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Configuration Caching Management Techniques for Reconfigurable Computing
Z. Li, K. Compton, and S. Hauck
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| Poster Session 1 |
| Paper Session 2 : Compilation I
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A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, and D. Zaretsky
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Stream-Oriented FPGA Computing in the Streams-C High Level Language
M. Gokhale, J. Stone, J. Arnold, and M. Kalinowski
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| Paper Session 3 : Applications I
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A Reconfigurable Computing Architecture for Microsensors
S. Scalera, M. Falco, and B. Nelson
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FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
K. Leung, K. Ma, W. Wong, and P. Leong
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Customizing Graphics Applications: Techniques and Programming Interface
H. Styles and W. Luk
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| Poster Session 2 |
| Paper Session 4 : Compilation II
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Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
P. Diniz and J. Park
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A C to HDL Compiler for Pipeline Processing on FPGAs
T. Maruyama and T. Hoshino
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| Thursday, April 18, 2000 |
| Paper Session 5 : Cryptographic Applications
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High Performance DES Encryption in VirtexTM FPGAs Using JbitsTM
C. Patterson
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A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA
M. Leong 0. Cheung, K. Tsoi, and P. Leong
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An Adaptive Cryptographic Engine for IPSec Architectures
A. Dandalis, V. Prasanna, and J. Rolim
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| Poster Session 3 |
| Paper Session 6 : Programming Tools
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Death of the RLOC?
S. Singh
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Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
P. James-Roxby and S. Guccione
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| Paper Session 7 : Fault Tolerance
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Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
J. Emmert, C. Stroud, B. Skaggs, and M. Abramovici
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An ACS Robotic Control Algorithm with Fault Tolerant Capabilities
S-Y. Yu, N. Saxena, and E. McCluskey
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Tunable Fault Tolerance for Runtime Reconfigurable Architectures
S. Sinha, P. Kamarchik, and S. Goldstein
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| Poster Session 4 |
| Paper Session 8 : Wireless Applications
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Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs
C. Dick, F. Harris, and M. Rice
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Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems
A. Alsolaim, J. Becker, M. Glesner, and J. Starzyk
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| Friday, April 19, 2000 |
| Paper Session 9 : Applications II
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Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
B. Levine, R. Taylor, and H. Schmit
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Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine
E. Sotiriades, A. Dollas, and P. Athanas
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An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
C. Ciressan, E. Sanchez, M. Rajman, and J-C. Chappelier
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| Poster Session 3 |
| Paper Session 10 : Applications III
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A Reliable LZ Data Compressor on Reconfigurable Coprocessors
W-J. Huang, N. Saxena, and E. McCluskey
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EVIDENCE: An FPGA-Based System for Photon Event IDENtification and CEntroiding
M. Alderighi, S. DÂ’Angelo, and G. Sechi
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Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware
M. Wirthlin, S. Morrison, P. Graham, and B. Bray
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