| Wednesday, April 15, 1998 |
| Paper Session 1 : Architectures I
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A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
T. Miyamori and K. Olukotun
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Exploring Optimal Cost-Performance Designs for Raw Microprocessors
C.A. Moritz, D. Yeung, and A. Agarwal
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The NAPA Adaptive Processing Architecture
C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale
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| Poster Session 1 |
| Paper Session 2 : Special Purpose Systems
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A Stream-Based Configurable Computing Radio Testbed
S. Swanchara, S. Harper, and P. Athanas
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Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation
A. Dollas, E. Sotiriades, and A. Emmanonelides
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| Paper Session 3 : Architectures II
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New FPGA Architecture for Bit-Serial Pipeline Datapath
A. Ohta, T. Isshiki, and H. Kunieda
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Plastic Cell Architecture: Towards Reconfigurable Computing for General Purpose
K. Nagami, K. Oguri, T. Shiozawa, H. Ito, and R. Konishi
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The Design and Implementation of a Context Switching FPGA
S.M. Scalera and J.R. Vazquez
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| Poster Session 2 |
| Paper Session 4 : Applications I
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A Run-Time Reconfigurable Engine for Image Interpolation
R. Hudson, D. Lehn and P. Athanas
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Hardware/Software Integration in Solar Polarimetry
M. Shand and L. Moll
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| Thursday, April 16, 1998 |
| Paper Session 5 : Compilers
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An Overview of the COBRA-ABS High Level Synthesis System for
Multi-FPGA Systems
A.A. Duncan, D.C. Hendry, P. Cray
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Specifying and Compiling Applications for RaPiD
D. Cronquist, P. Franklin, S. Berg and C. Ebeling
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NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
M.B. Gokhale and J.M. Stone
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| Poster Session 3 |
| Paper Session 6 : Tools for Run Time Reconfiguration
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Configuration Compression for the Xilinx XC6200 FPGA
S. Hauck, Z. Li and E. Schwabe
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Automating Production of Run-Time Reconfigurable Designs
N. Shirazi, W. Luk and P.Y.K. Cheung
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| Paper Session 7 : Module Generation
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Object Oriented Circuit-Generators in Java
M. Chu, K. Sulimma, N. Weaver, A. DeHon, J. Wawrzynek
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PAM-Blox: High Performance FPGA Design for Adaptive Computing
O. Mencer, M. Morf and M. J. Flynn
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JHDL - An HDL for Reconfigurable Systems
P. Bellows and B. Hutchings
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| Poster Session 4 |
| Paper Session 8 : Applications II
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Accelerating Boolean Satisfiability with Configurable Hardware
P. Zhong, M. Martonosi, P. Ashar and S. Malik
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Dynamic Circuit Generation for Solving Specific Problem
Instances of Boolean Satisfiability
A. Rashid, J. Leonard and W.H. Mangione-Smith
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| Friday, April 17, 1998 |
| Paper Session 9 : Arithmetic
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A Re-evaluation of the Practicality of Floating Point
Operations on FPGAs
W. Ligon, S. McMillan, G. Monn, F. Stivers and K. Underwood
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A Variable Long-precision Arithmetic Unit Design suitable for
Reconfigurable Coprocessor Architectures
A. F. Tenca and M. D. Ercegovac
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A Reconfigurable Multiplier Array for Video Image Processing
Tasks, Suitable for Embedding in an FPGA Structure
S. D. Haynes and P. Y. K. Cheung
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| Poster Session 5 |
| Paper Session 10 : Applications III
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Accelerating Adobe Photo Using the XC6200 FPGA
S. Singh and R. Sloys
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Analysis of the XC6000 Architecture for Embedded System Design
K. Weiss, R. Kistner, A. Kunzmann, W. Rosenstiel
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