FCCM 2015 -- IEEE Symposium on Field-Programmable Custom Computing Machines

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Programme Venue Registration and Accommodation Sunday Workshop

FCCM 2015

The 23rd IEEE International Symposium on
Field-Programmable Custom Computing Machines

May 3-5, Vancouver, British Columbia, Canada

Vancouver at Sunset by Alan Bruce (flickr, CC)

Vancouver at Sunset by Alan Bruce (flickr, CC)

Sunday 3rd May
08:00 - 12:00	Cypress PSoC Workshop
14:00 - 14:45	Registration
14:45 - 15:00	Welcome Remarks
15:00 - 19:00	Workshop on the Internet of Things
19:00 - 21:00	FCCM 2015 Opening Reception

Monday 4th May - Day 1
07:45 - 08:40	Breakfast and Registration
08:40 - 09:00	Welcoming Remarks
09:00 - 09:55	Paper Session M1 : Trends and overlay architectures
09:55 - 11:00	Poster Session P1
11:00 - 12:10	Paper Session M2 : Networking and Compression
12:10 - 13:45	Lunch
13:45 - 14:50	Paper Session M3 : Power and Energy
14:50 - 15:50	Poster Session P2
15:50 - 16:40	Paper Session M4 : Machine Learning techniques
16:50 - 18:30	...
18:30 - 21:00	Demo Night

Tuesday 5th May - Day 2
08:40 - 09:55	Paper Session T1 : Debug, Test and Fault Detection
09:55 - 11:00	Poster Session P3
11:00 - 12:15	Paper Session T2 : Applications
12:15 - 13:45	Lunch
13:45 - 14:35	Paper Session T3 : Implementation I
14:35 - 15:30	Poster Session P4
15:30 - 16:20	Paper Session T4 : Implementation II
16:20 - 16:45	Best Paper Award and Closing Remarks
Wednesday 6th May + Thursday 7th May
Xilinx Advanced Embedded System Design on Zynq using Vivado

Demo Night

Each year we have an informal show-and-tell called Demo Night. This year it's Monday evening, May 4, 2015 at 18:30. Paper and poster authors and commercial vendors bring their FCCMs, hardware, gateware, slideware, software, tools, chips, and set up demos. Attendees circulate, enjoy the demos, and engage with the presenters while enjoying the food and drink at this stand-up and learn event. It's always informative for demoers and demoees, great networking, and lots of fun too. For more information about exhibiting, see the demo night invitation.

Technical Programme : Papers

Slides

Monday 4th May
07:45 - 08:40	Breakfast and Registration
08:40 - 09:00	Welcoming Remarks
09:00 - 09:50	Paper Session M1 : Trends, Revisits and Overlays Chair: Ken Eguro
09:00 - 09:20 Slides	Technology Scaling in FPGAs: Trends in Applications and Architectures Lesley Shannon, Veronica Cojocaru, Cong Nguyen Dao and Philip H.W. Leong
09:20 - 09:40	Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs Aaron Landy and Greg Stitt
09:40 - 09:45	Rapid Overlay Builder for Xilinx FPGAs Michael Yue, Dirk Koch and Guy Lemieux
09:45 - 09:50	Adjustable-Cost Overlays for Runtime Compilation James Coole and Greg Stitt
09:50 - 09:55	Efficient Overlay Architecture Based on DSP Blocks Abhishek Jain, Suhaib Fahmy and Douglas Maskell
09:55 - 11:00	Poster Session P1
11:00 - 12:10	Paper Session M2 : Networking and Compression Chair: Mike Wirthlin
11:00 - 11:20 Slides	Scalable 10 Gbps TCP/IP Stack Architecture for Reconfigurable Hardware David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees Vissers, and Raymond Carley
11:20 - 11:40 Slides	Enabling High Throughput and Virtualization for Traffic Classification on FPGA Yun R. Qu and Viktor K. Prasanna
11:40 - 12:00	A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs Jeremy Fowers, Joo-Young Kim, Doug Burger and Scott Hauck
12:00 - 12:05 Slides	Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a single FPGA Thiem Van Chu, Shimpei Sato and Kenji Kise
12:05 - 12:10 Slides	Accelerating SpMV on FPGAs by Compressing Nonzero Values Paul Grigoras, Pavel Burovskiy, Eddie Hung and Wayne Luk
12:10 - 13:45	Lunch
13:45 - 14:50	Paper Session M3 : Power and Energy Chair: Jason Anderson
13:45 - 14:05	Zedwulf: Power-Performance Tradeoffs of a 32-node Zynq SoC Cluster Pradeep Moorthy and Nachiket Kapre
14:05 - 14:25	Energy-Efficient Acceleration of OpenCV Saliency Computation using Soft Vector Processors Gopalakrishna Hegde and Nachiket Kapre
14:25 - 14:45	Autotuning FPGA Design Parameters for Performance and Power Azamat Mametjanov, Prasanna Balaprakash, Chekuri Choudary, Paul D. Hovland, Stefan M. Wild and Gerald Sabin
12:45 - 14:50	FIR Filter Based on Stochastic Computing with Reconfigurable Digital Fabric Mohammed Alawad and Mingjie Lin
14:50 - 15:50	Poster Session P2
15:50 - 16:50	Paper Session M4 : Machine Learning Techniques Chair: Guy Lemieux
15:50 - 16:10	Pipelined Genetic Progagation Liucheng Guo, Ce Guo, David Thomas and Wayne Luk
16:10 - 16:30	FPGA Acceleration of Recurrent Neural Network Based Language Model Sicheng Li, Chunpeng Wu, Hai (Helen) Li, Boxun Li, Yu Wang and Qinru Qiu
16:30 - 16:50	Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing Nachiket Kapre, Bibin Chandrashekharan, Harnhua Ng and Kirvy Teo
18:30 - 21:00	Demo Night
Tuesday 5th May
08:40 - 09:55	Paper Session T1 : Debug, Test and Fault Detection Chair: Peter Cheung
08:40 - 09:00	Winner of the Best Paper Award: Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs Jeffrey Goeders and Steve J.E. Wilton
09:00 - 09:20	High-Level Debugging and Verification for FPGA-Based Multicore Architectures Oriol Arcas Abella, Adrián Cristal and Osman S. Unsal
09:20 - 09:40	Estimating Soft Processor Soft Error Sensitivity through Fault Inection Nathan A. Harward, Michael R. Gardiner, Luke W. Hsiao and Michael J. Wirthlin
09:40 - 09:45	Protecting Against Cryptographic Trojans in FPGAs, Pawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux and Russell Tessier
09:45 - 09:50 Slides	Automatic High-Level Checkpoint Selection for Reconfigurable Systems Alban Bourge, Olivier Muller and Frédéric Rousseau
09:50 - 09:55 Slides	Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS Junyi Liu, Samuel Bayliss and George A. Constantinides
9:55 - 11:00	Poster Session P3
11:00 - 12:15	Paper Session T2 : Applications Chair: Nachiket Kapre
11:00 - 11:20 Slides	Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk and T.N. Palmer
11:20 - 11:40 Slides	Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates Roger Moussalli, Mudhakar Srivatsa and Sameh Asaad
11:40 - 12:00 Slides	SSketch:An Automated Framework for Streaming Sketch-based Analysis of Big Data on FPGA Bita Darvish Rouhani, Ebrahim M. Songhori, Azalia Mirhoseini and Farinaz Koushanfar
12:00 - 12:05	An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures Jens Korinth, David de La Chevallerie and Andreas Koch
12:05 - 12:10	A Novel High-Throughput Acceleration Engine for Read Alignment Yu-Ting Chen, Jason Cong, Jie Lei and Peng Wei
12:10 - 12:15	A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data Storages Dongyang Li, Qing Yang, Qingbo Wang, Cyril Guyot, Ashwin Narasimha, Dejan Vucinic and Zvonimir Bandic
12:15 - 13:45	Lunch
13:45 - 14:35	Paper Session T3 : Implementation I Chair: André DeHon
13:45 - 14:05 Slides	Modular SRAM-Based Binary Content-Addressable Memories Ameer M.S. Abdelhadi and Guy G.F. Lemieux.
14:05 - 14:25	A Low-Latency, Low-Area Hardware Oblivious RAM Controller Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos and Srinivas Devadas
14:25 - 14:30	Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area Farheen Khan and Andy Ye
14:30 - 14:35 Slides	Offset Pipelined Scheduling: Conditional Branching for CGRAs Aaron Wood and Scott Hauck
14:35 - 15:30	Poster Session P4
15:30 - 16:20	Paper Session T4 : Implementation II Chair: Kyle Rupnow
15:30 - 15:50	Optimizing Residue Number Reverse Converters through Bitwise Arithmetics on FPGAs Bangtian Liu, Haohuan Fu, Lin Gan, Wenlai Zhao and Guangwen Yang
15:50 - 16:10 Slides	A Reconfigurable Multiclass Support Vector Machine Architecture for Real-Time Embedded Systems Classification Jason Kane, Robert Hernandez and Qing Yang
16:10 - 16:15 Slides	Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection Marco Rabozzi, Antonio Miele and Marco D. Santambrogio
15:15 - 16:20	Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions Victor M. Gonçalves Martins, João Gabriel Reis, Horácio C.C. Neto and Eduardo Augusto Bezerra
16:20 - 16:45	Best Paper Award and Closing Remarks

Technical Programme : Posters

Monday 4th May
07:45 - 08:40	Breakfast and Registration
08:40 - 09:00	Welcoming Remarks
09:00 - 09:50	Paper Session M1 : Trends, Revisits and Overlays
09:55 - 11:00	Poster Session P1
	Rapid Overlay Builder for Xilinx FPGAs Michael Yue, Dirk Koch and Guy Lemieux
	Adjustably Flexible, Low-Overhead Overlays for Runtime FPGA Compilation James Coole and Greg Stitt
	Efficient Overlay Architecture Based on DSP Blocks Abhishek Jain, Suhaib Fahmy and Douglas Maskell
	High Performance Sparse LU Solver FPGA Accelerator using a Static Synchronous Data Flow Model Mohamed W. Hassan, Ahmed E. Helal and Yasser Y. Hanafy
	Cycle-Accurate Replay and Debugging of Running FPGA Systems Sunil Shukla and David F. Bacon
	Heterogeneous Platform to Accelerate Compute Intensive Applications Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman Unsal and Adrian Cristal
	High Performance Memory Accesses on FPGA-SoCs: A quantitative analysis Matthias Göbel, Chi Ching Chi, Mauricio Alvarez-Mesa and Ben Juurlink
	Sparse Graph Processing with Soft Processors Nachiket Kapre
	Improving Data Partitioning Performance on OpenCL-based FPGAs Zeke Wang, Bingsheng He and Wei Zhang
	Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs Hongyuan Ding and Miaoqing Huang
11:00 - 12:10	Paper Session M2 : Networking and Compression
12:10 - 13:45	Lunch
13:45 - 14:50	Paper Session M3 : Power and Energy
14:50 - 15:30	Poster Session P2
	Energy-Efficient High Order FIR Filtering through Reconfigurable Stochastic Processing Mohammed Alawad and Mingjie Lin
	Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a single FPGA Thiem Van Chu, Shimpei Sato and Kenji Kise
	Lossless Value Compression for Sparse matrix Vector Multiplication on FPGAs Paul Grigoras, Pavel Burovskiy, Eddie Hung and Wayne Luk
	Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim Garside and Mikel Luján
Poster	Fast Design Space Exploration using Vivado HLS: Non-Binary LDPC Decoders Joao Andrade, Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne and Gabriel Falcao
	Design of A Distributed Compressor for Astronomy SSD Bo Peng, Xi Jin, Tianqi Wang, Xueliang Du
	Scalable Key/Value Search in Datacenters John W. Lockwood
	Function Proxies for Improved Resource Sharing and High Level Synthesis Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo and Fabrizio Ferrandi
	Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs Cheng Liu and Hayden Kwok-Hay So
	Adaptive Configurable Transactional Memory for Multi-Processor FPGA Platforms Jeevan Sirkunan, Chia Yee Ooi, N. Shaikh-Husin, Yuan Wen Hau, M. N. Marsono
15:50 - 16:50	Paper Session M4 : Machine Learning Techniques
18:30 - 21:00	Demo Night
Tuesday 5th May
08:40 - 09:55	Paper Session T1 : Debug, Test and Fault Detection
9:55 - 11:00	Poster Session P3
	Protecting Against Cryptographic Trojans in FPGAs Pawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux and Russell Tessier
	Automatic High-Level Checkpoint Selection for Reconfigurable Systems Alban Bourge, Olivier Muller and Frédéric Rousseau
	Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS Junyi Liu, Samuel Bayliss and George Constantinides
	Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection Marco Rabozzi, Antonio Miele and Marco Domenico Santambrogio
	Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions Victor Martins, João Reis, Horacio Neto and Eduardo Bezerra
	HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA Behzad Salami, Oriol Arcas-Abella and Nehir Sonmez
	Accelerating Big Data Analytics Using FPGAs Katayoun Neshatpour, Maria Malik, Mohammad Ali Ghodrat and Houman Homayoun
	Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System Venkatasubramanian Viswanathan, Rabie Ben Atitallah and Jean-Luc Dekeyser
	A System on Reconfigurable Chip for Handwritten Digit Recognition Luca B. Saldanha and Christophe Bobda
	An efficient KNN algorithm implemented on FPGA based heterogeneous computing system using OpenCL Yuliang Pu, Jun Peng, Letian Huang, and John Chen
11:00 - 12:15	Paper Session T2 : Applications
12:15 - 13:45	Lunch
13:45 - 14:35	Paper Session T3 : Implementation I
14:35 - 15:30	Poster Session P4
	An Open Source Tool Flow for the Composition of Reconfigurable hardware Thread Pool Architectures Jens Korinth, David de La Chevallerie and Andreas Koch
	A Novel High-Throughput FPGA Acceleration Engine for Read Alignment Yu-Ting Chen, Jason Cong, Jie Lei and Peng Wei
	A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data Storages Dongyang Li, Qingbo Wang, Cyril Guyot, Ashwin Narasimha, Dejan Vucinic, Zvonimir Bandic and Qing Yang
	Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area Farheen Khan and Andy Ye
	Offset Pipelined Scheduling: Conditional Branching for CGRAs Aaron Wood and Scott Hauck
	A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin Hand, Robert Carlson, and Emre Ozer
	FPGA Design for PCANet Deep Learning Network Yuteng Zhou, Wei Wang, and Xinming Huang
	Functional Locking Modules for Design Protection of Intellectual Property Cores Brice Colombier and Lilian Bossuet
	Virtual Channel and Switch Allocation for Low latency Network-on-Chip Routers Alireza Monemi, Chia Yee Ooi and Muhammad Nadzir Marsono
	Early experiences with OpenCL on FPGAs: convolution case study C. Rodriguez-Donate, G. Botella, C. Garcia, E. Cabal-Yepez, M. Prieto-Matias
15:30 - 16:20	Paper Session T4 : Implementation II
16:20 - 16:45	Best Paper Award and Closing Remarks