| Wednesday, April 21, 1999 |
| Paper Session 1 : Tools
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Macro-Based Hardware Compilation of Java(tm) Bytecodes into a
Dynamic Reconfigurable Computing System
Joao M. P. Cardoso and Horacio C. Neto
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A CAD Suite for High-Performance FPGA Design
Brad Hutchings, et. al.
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Formal Verification of Reconfigurable Cores
Satnam Singh and Carl Johan Block
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| Poster Session 1 |
| Paper Session 2 : Network Applications
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Transmutable Telecom System and Its Application
T. Miyazaki, T. Murooka, M. Katayama, A. Takahara
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Implementation and Evaluation of a Prototype Reconfigurable Router
Jason Hess, David Lee, Scott Harper, Mark Jones and Peter Athanas
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| Paper Session 3 : Compilation
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Pipeline Vectorization for Reconfigurable Systems
Markus Weinhardt and Wayne Luk
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Automatic Allocation of Arrays to Memories in FPGA Processors
With Multiple Memory Banks
Maya Gokhale and Jan Stone
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Parallelizing Applications into Silicon
Jonathan Babb et. al.
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| Poster Session 2 |
| Paper Session 4 : Architectures
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Reconfigurable Elements for a Video Pipeline Processor
Michael Piacentino, Gooitzen van der Wal and Michael Hansen
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ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
Bernardo Kastrup, Arjan Bink and Jan Hoogerbrugge
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| Thursday, April 22, 1999 |
| Paper Session 5 : Tools
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CPR: A Configuration Profiling Tool
Srihari Cadambi and Seth Copen Goldstein
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Debugging Techniques for Dynamically Reconfigurable Hardware
Nicholas McKay and Satnam Singh
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Improving Simulation Accuracy in Design Methodologies
for Dynamically Reconfigurable Logic Systems
Milan Vasilko and David Cabanis
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| Poster Session 3 |
| Paper Session 6 : Graphics Applications
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Reconfigurable Computing for Augmented Reality
W. Luk, T.K. Lee,
J.R. Rice, N. Shirazi and P.Y.K. Cheung
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Sepia: scalable 3D compositing using PCI Pamette
Laurent Moll, Alan Heirich and Mark Shand
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| Invited Talk
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Molecular Manufacturing: Beyond Moore's Law
Philip Kuekes
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| Paper Session 7 : Applications
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An Edge-Endpoint-Based Configurable Hardware Architecture for
VLSI CAD Layout Design Rule Checking
Zhen Luo, Margaret Martonosi, Pranav Ashar
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Fafner--Accelerating Nesting Problems with FPGAs
J. Carlos Alves et. al.
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| Poster Session 4 |
| Paper Session 8 : DSP Applications
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Field Programmable Gate Array Based Radar Front-End
Digital Signal Processing
Tyler Moeller and David R. Martinez
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Optimizing FPGA-based vector product designs
Daniel Benyamin, Wayne Luk and John Villasenor
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| Friday, April 23, 1999 |
| Paper Session 9 : Run Time Systems
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PCI-PipeRench and the SwordAPI: A System for Stream-based
Reconfigurable Computing
Ronald Laufer, R. Reed Taylor and Herman Schmit
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Safe and Protected Execution for the Morph/AMRM
Reconfigurable Processor
Andrew A. Chien and Jay H. Byun
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Implementing an API for Distributed Adaptive Computing Systems
Mark Jones et. al.
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| Poster Session 5 |
| Paper Session 10 : Arithmetic
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A Super-Serial Galois Fields Multiplier for FPGAs and
its Application to Public-Key Algorithms
Gerardo Orlando and Christof Paar
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Automatic Floating to Fixed Point Translation
and its Application to Post--Rendering 3D Warping
M. P. Leong et. al.
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Dynamic Precision Management for Loop Computations on
Reconfigurable Architectures
Kiran Bondalapati and Viktor K. Prasanna
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