Each year we have an informal show-and-tell called Demo Night. This year it's Monday evening,
May 1, 2017 at 18:30. Paper and poster authors and commercial vendors bring their FCCMs,
hardware, gateware, slideware, software, tools, chips, and set up demos. Attendees circulate, enjoy
the demos, and engage with the presenters while enjoying the food and drink at this stand-up and
learn event. It's always informative for demoers and demoees, great networking, and lots of fun
too.
| Monday 2nd May |
| 07:45 - 08:40 | Breakfast and Registration |
| 08:40 - 09:00 | Welcoming Remarks |
| 09:00 - 09:50 | Paper Session M1 : Applications (Big Data)
Chair: TBD |
09:00 - 09:20
|
High-Performance Hardware Merge Sorter
Susumu Mashimo, Thiem Van Chu and Kenji Kise |
| 09:20 - 09:40 |
Communication-Aware MCMC Method for Big Data Applications on FPGAs
Shuanglong Liu and Christos Bouganis |
| 09:40 - 10:00 |
Terabyte Sort on FPGA-Accelerated Flash Storage
Sang-Woo Jun, Shuotao Xu and Arvind Arvind |
| 10:00 - 11:00 | Poster Session P1 |
| 11:00 - 11:45 | Paper Session M2 : Overlays
Chair: TBD |
11:00 - 11:20
|
On Bit-Serial NoCs for FPGAs
Nachiket Kapre |
11:20 - 11:40
|
Implementing FPGA overlay NoCs using the Xilinx UltraScale memory cascades
Nachiket Kapre |
| 11:40 - 12:00 |
Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration
Ashutosh Dhar and Deming Chen |
| 12:00 - 13:15 | Lunch |
| 13:15 - 13:30 | Announcements |
| 13:35 - 14:50 | Paper Session M3 : Applications (Physics and Biology)
Chair: TBD |
| 13:30 - 13:50 |
An Architecture for the Acceleration of a hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor
Emmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou, Dionisios N Pnevmatikatos, Athanasia Papoutsi, Panagiotis C. Petrantonakis, Panayiota Poirazi, Spyridon Chavlis and George Kastellakis |
| 13:50 - 14:10 |
FPGA-based Real-time Charged Particle Trajectory Reconstruction at the Large Hadron Collider
Louise Skinnari, Anders Ryd, Zhiru Zhang, Jorge Chaves, Margaret Zientek, Zhengcheng Tao, Charles Strohman, Yuri Gershtein, Eva Halkiadakis, Savvas Kyriacou, Edward Bartz, Robert Stone, Brian Winer, Anthony Lefeld, Michael Hildreth, Kevin Lannon and Peter Wittich |
| 14:10 - 14:15 |
Bonded Force Computations on FPGAs
Qingqing Xiong and Martin Herbordt |
| 14:15 - 14:20 |
Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulations
Almomany Abedalmuhdi, B. Earl Wells and Ken-Ichi Nishikawa |
| 14:20 - 15:20 | Poster Session P2 |
| 15:20 - 16:20 | Paper Session M4 : Applications (Machine Learning)
Chair: TBD |
| 15:20 - 15:40 |
Customizing Neural Networks for Efficient FPGA Implementation
Mohammad Samragh, Mohammad Ghasemzadeh and Farinaz Koushanfar |
| 15:40 - 16:00 |
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer
Yongming Shen, Michael Ferdman and Peter Milder |
| 16:00 - 16:20 |
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs
Liqiang Lu, Yun Liang, Qingcheng Xiao and Shengen Yan |
| 16:20 | Announcements |
| 18:30 - 21:00 | Demo Night |
| Tuesday 2nd May |
| 08:40 - 09:00 | Announcements |
09:00 - 09:50
| Paper Session T1 : High Level Synthesis
Chair: TBA |
| 09:00 - 09:20 |
Using Runahead Execution to Hide Memory Latency in High Level Synthesis
Shane Fleming and David Thomas |
| 09:20 - 09:25 |
Energy Efficient Loop Unrolling for Low-Cost FPGAs
Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel Holcomb and Russell Tessier |
| 09:25 - 09:30 |
Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs
Andrew Schmidt, Gabriel Weisz and Matthew French |
| 09:30 - 09:35 |
HLS-Based Performance Debugging for FPGA Designs
Young-Kyu Choi and Jason Cong |
| 09:35 - 09:40 |
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS
Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin and Oliver Diessel |
| 9:40 - 10:10 | Poster Session P3 |
| 10:10 - 10:50 | Paper Session T2 : Test and Debug
Chair: TBA |
10:10 - 10:30
|
Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices
Jeffrey Goeders |
10:30 - 10:50
|
The potential of dynamic binary modification and CPU/FPGA SoCs for simulation
John Mawer, Oscar Palomar, Cosmin Gorgovan, Andy Nisbet, Will Toms and Mikel Lujan |
| 10:50 - 11:10 | Coffee Break |
| 11:10 - 12:15 | Paper Session T3 : Applications (Machine Learning 2)
Chair: TBA |
11:10 - 11:30
|
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang and Jason Cong |
11:30 - 11:50
|
FPGA accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-off
Kaan Kara, Ce Zhang and Gustavo Alonso |
11:50 - 11:55
|
A Configurable FPGA Implementation of the Tanh Function using DCT Interpolation
Ahmed Abdelsalam, Pierre Langlois and Farida Cheriet |
| 12:15 - 13:10 | Lunch |
| 13:10 - 13:40 | Announcements and Best Paper Award |
| 13:40 - 14:25 | Paper Session T4 : CAD Tools
Chair: TBA |
13:40 - 14:00
|
ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding
Chin Hau Hoo and Akash Kumar |
14:00 - 14:20
|
Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures
Jack Wadden, Samira Khan and Kevin Skadron |
14:20 - 14:25
|
Relocating Encrypted Partial Bitstreams by Advance Task Address Loading
Adewale Adetomi, Godwin Enemali and Tughrul Arslan |
| 14:25 - 15:25 | Poster Session P4 |
| 15:25 - 16:45 | Paper Session T5 : Applications (Big Data 2)
Chair: TBA |
15:25 - 15:45
|
K-mer Counting Using Bloom Filters with an FPGA-Attached HMC
Nathaniel Mcvicar, Chih-Ching Lin and Scott Hauck |
15:45 - 16:05
|
Centaur: A Framework for Hybrid CPU-FPGA Databases
Muhsen Owaida, David Sidler, Kaan Kara and Gustavo Alonso |
16:05 - 16:25
|
Scalable Network Function Virtualization for Heterogeneous Middleboxes
Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao and Russell Tessier |
16:25 - 16:45
|
A Nanosecond-level Hybrid Table Design for Financial Market Data Generators
Haohuan Fu, Conghui He, Wayne Luk, Weijia Li and Guangwen Yang |
| 16:45 | Closing Remarks |
| Monday 1st May |
| 07:45 - 08:40 | Breakfast and Registration |
| 08:40 - 09:00 | Welcoming Remarks |
| 09:00 - 10:00 | Paper Session M1 : Applications (Big Data) |
| 10:00 - 11:00 | Poster Session P1 |
|
S2FA: A Configurable Hardware Accelerator Compilation Framework for Energy-Efficient Computing in Datacenters
Cody Hao Yu, Max Grossman, Peng Wei, Peng Zhang, Vivek Sarkar and Jason Cong |
|
Improved Synthesis of Compressor Trees on FPGAs in High-level Synthesis
Le Tu, Yuelai Yuan, Kan Huang, Xiaoqiang Zhang, Zixin Wang and Dihu Chen |
|
FPGA based Efficient Shuffling Scheme for DPA-resistant AES via Instruction Set Extension
Yi Wang and Yajun Ha |
|
SDSoC Trace: A Higher Abstraction for System-Level Profiling, Debugging, and Tracing of MPSoC Systems
Sam Skalicky, Jim Hwang and Vinod Kathail |
|
Swif: A Simplified Workload-centric Framework for Heterogeneous Computing
David Ojika, Piotr Majcher, Wojciech Neubauer, Suchit Subhaschandra and Darin Acosta |
|
Megrez: Parallelizing FPGA Routing Based on Strictly-Ordered Partitioning
Minghua Shen and Guojie Luo |
|
An FPGA Design Framework for CNN Sparsification and Acceleration
Sicheng Li, Wei Wen, Yu Wang, Song Han, Yiran Chen and Hai Li |
|
On the Resilience of FPGA-Based Deep Learning Accelerators
Behzad Salami, Adrian Cristal Kestelman and Osman Unsal |
|
Monitoring Sub-component Dynamic Power and Total Leakage on FPGA based SoCs
Young Cho |
|
FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters
Qiang Liu and Hanjing Qian |
|
Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker and Thilo Pionteck |
|
Exploration of OpenCL for FPGAs using SDAccel and Comparison to GPUs and Multicore CPUs
Lester Kalms and Diana Göhringer |
|
Scheduling Considerations for Voter Checking in TMR-MER Systems
Nguyen Nguyen, Ediz Cetin and Oliver Diessel |
|
A study on the cooling performance of microchannels in the context of FPGA based systems.
Girish Deshpande and Dinesh Bhatia |
|
Bit-width Based Resource Partitioning for CNN Acceleration on FPGA
Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu and Shaojun Wei |
|
High-Level Synthesis for Side-Channel Defense
Sven Tenzing Choden Konigsmark, Deming Chen and Martin D. F. Wong |
|
High-Level Synthesis of Datacenter Services
Justin Tai and Paul Chow |
| 11:00 - 12:05 | Paper Session M2 : Overlays |
| 12:05 - 13:15 | Lunch |
| 13:15 - 13:30 | Announcements |
| 13:30 - 14:20 | Paper Session M3 : Applications (Physics and Biology) |
| 14:20 - 15:20 | Poster Session P2 |
|
Bonded Force Computations on FPGAs
Qingqing Xiong and Martin Herbordt |
|
Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation
Almomany Abedalmuhdi, B. Earl Wells and Ken-Ichi Nishikawa |
|
PolyPC: Polymorphic Parallel Computing Framework on Embedded Reconfigurable System
Hongyuan Ding and Miaoqing Huang |
|
Evaluating FPGAs for HPC Applications with Irregular Memory Access Patterns using OpenCL
Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci-Memik, Gokhan Memik, Hal Finkel and Franck Cappello |
|
FPGA Acceleration of Multilevel ORB Feature Extraction for Computer Vision
Josh Weberruss, Lindsay Kleeman, David Boland and Tom Drummond |
|
Exploring the Potential of Reconfigurable Platforms for Order Book Update
Conghui He, Haohuan Fu, Wayne Luk, Weijia Li and Guangwen Yang |
|
Accelerating Graph Algorithms Through Efficient Storage and Access
Soroosh Khoram, Jialiang Zhang, Maxwell Strange and Jing Li |
|
Deploying FPGAs to Future-proof Genome-wide Analyses based on Linkage Disequilibrium
Dimitrios Bozikas, Nikolaos Alachiotis, Pavlos Pavlidis, Euripides Sotiriades and Apostolos Dollas |
|
A high-level synthesis approach optimizing accumulation-based programs into custom formats and operators
Yohann Uguen, Florent de Dinechin and Steven Derrien |
|
Phase Calibrated Physical Unclonable Function Design and Implementation on FPGAs
Wei Yan, Chenglu Jin, Fatemeh Tehranipoor and John Chandy |
|
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics
Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich and Stefan Wildermann |
|
Towards Timing Closure in High-Level Synthesis
Marco Lattuada and Fabrizio Ferrandi |
|
A Case for Common-Case: On FPGA Acceleration of Erasure Coding
Reza Nakhjavani and Jianwen Zhu |
|
Energy-driven Accelerator Exploration for Heterogeneous Multiprocessor Architectures
Baptiste Roux, Matthieu Gautier, Olivier Sentieys and Jean-Philippe Delahaye |
|
A CPU Interlay for Run-time Instruction Set Extensions
Jose Raul Garcia Ordaz and Dirk Koch |
|
A Parameterizable Activation Function Generator for FPGA-based Neural Network Applications
Sam Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang and Hayden Kwok-Hay So |
| 15:20 - 16:20 | Paper Session M4 : Applications (Machine Learning) |
| 18:30 - 21:00 | Demo Night |
| Tuesday 2nd May |
| 09:00 - 09:40 | Paper Session T1 : High Level Synthesis |
| 9:40 - 10:10 | Poster Session P3 |
|
Energy Efficient Loop Unrolling for Low-Cost FPGAs
Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel Holcomb and Russell Tessier |
|
Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs
Andrew Schmidt, Gabriel Weisz and Matthew French |
|
HLS-Based Performance Debugging for FPGA Designs
Young-Kyu Choi and Jason Cong |
|
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS
Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin and Oliver Diessel |
|
One Size Does Not Fit All: Implementation Trade-Offs for Iterative Stencil Computations on FPGAs
Gaël Deest, Tomofumi Yuki, Sanjay Rajopadhye and Steven Derrien |
|
Energy-efficient Accelerator for Collaborative Filtering on FPGA
Shijie Zhou and Viktor Prasanna |
|
Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board
Jong Hun Han, Neelakandan Manihatty-Bojan and Andrew Moore |
|
An efficient out-of-order load-store queue for spatial computing
Lana Josipovic, Philip Brisk and Paolo Ienne |
|
Latency-Driven Design for FPGA-based Convolutional Neural Networks
Stylianos Venieris and Christos Bouganis |
|
Validating Optimisations for Chaotic Stencil Computations
James Targett, Wayne Luk and Peter Duben |
|
Optimising stochastic gradient decent for training classifiers
Ce Guo and Wayne Luk |
|
Fast and Efficient Implementation of Convolutional Neural Networks on FPGA
Abhinav Podili, Chi Zhang and Viktor Prasanna |
|
Fine-grained Acceleration of Binary Neural Networks using Intel® Xeon® Processor with Integrated FPGA
Philip Colangelo, Randy Huang, Enno Luebbers, Martin Margala and Kevin Nealis |
|
Dense Fixed-point Matrix Multiplication on FPGAs
Randy Huang, Jason Ong and Yeong-Tat Liew |
|
Mapping Programmable Network Packet Pipelines to HMC-Enabled FPGAs
Jehandad Khan and Peter Athanas |
|
CGRA-ME: A Unified Framework forCGRA Modelling and Exploration
S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin-Hee Kim, Yuko Hara Azumi and Jason Anderson |
|
Implementation of Selected Lightweight Cryptographic Ciphers in a Custom-Designed Reconfigurable Processor
William Diehl and Kris Gaj |
| 10:10 - 10:50 | Paper Session T2 : Test and Debug |
| 11:10 - 12:15 | Paper Session T3 : Applications (Machine Learning 2) |
| 12:15 - 13:10 | Lunch |
| 13:40 - 14:25 | Paper Session T4 : CAD Tools |
| 14:25 - 15:25 | Poster Session P4 |
|
CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada and Yasuhiko Nakashima |
|
A Configurable FPGA Implementation of the Tanh Function using DCT Interpolation
Ahmed Abdelsalam, Pierre Langlois and Farida Cheriet |
|
Relocating Encrypted Partial Bitstreams by Advance Task Address Loading
Adewale Adetomi, Godwin Enemali and Tughrul Arslan |
|
Multi-FPGA Evaluation Platform for Disaggregated Computing
Dimitris Theodoropoulos, Nikolaos Alachiotis and Dionisios Pnevmatikatos |
|
An FPGA-Quantum Annealer Hybrid System for Wide-Band RF Detection
Zachary Baker |
|
An Incremental Approach for In-System FPGA Debugging of High-Level Synthesis Circuits
Pavan Kumar Bussa, Jeffrey Goeders and Steven J.E. Wilton |
|
Dynamic Module Partitioning for Library based Placement on Heterogeneous FPGAs
Fubing Mao, Wei Zhang, Bingsheng He and Siew Kei Lam |
|
Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data Processing
Qian Wu, Yongxin Zhu and Xu Wang |
|
FeatherNet: A Minimalist Design for Accelerating Convolutional Neural Networks for Low-end FPFA Platforms
Raghid Morcel, Haitham Akkary, Hazem Hajj, Mazen Saghir, Anil Keshavamurthy, Rahul Khanna and Hassan Artail |
|
A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs
Ian Barge and Cristinel Ababei |
|
HLS Compilation for CPU Interlays
Jose Raul Garcia Ordaz and Dirk Koch |
|
Applying The Flask Security Architecture to Secure SoC Design
Festus Hategekimana and Christophe Bobda |
|
A Real-time Embedded FPGA Processor for a Stand-alone Dual-Mode Assistive Device
Ali Jafari, Maysam Ghovanloo and Tinoosh Mohsenin |
|
CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP Security
Taylor Whitaker and Christophe Bobda |
|
volo: A Vector Overlay To Accelerate YOLO, A CNN-based Multi-Object Detection System
Joe Edwards, Aaron Severance, Joel Vandergriendt, Ken Eguro and Guy Lemieux |
|
A Scalable FPGA-based Accelerator for High Throughput MCMC Algorithms
Morteza Hosseini, Rashidul Islam, Amey Kulkarni and Tinoosh Mohsenin |
|
Improving the Accuracy of Arctan for Face Detection
Youngsoo Kim, Hossein Shahdoost, Shrikant Jadhav and Clay S. Gloster |
|
Out with the Old? Evaluating FPGA Parameterizable Clusters
Grace Zgheib, Eliéva Pignat and Paolo Ienne |
|
A GPU-like Programming Paradigm for Floating-Point Arithmetic on FPGAs
Muhammed Al Kadi, Benedikt Janssen and Michael Huebner |
|
Exploring the Performance of Partially Reconfigurable Point-to-Point Interconnects
El Mehdi Abdali, Maxime Pelcat, François Berry, Jean-Philippe Diguet and Francesca Palumbo |
| 15:25 - 16:45 | Paper Session T5 : Applications (Big Data 2) |
| 16:45 | Closing Remarks |