| Monday, April 22, 2002 |
| Paper Session 1 : Applications I
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Image Registration of real-time video data using the SONIC reconfigurable computer platform
Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk, Jason Pelly
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A Massively Parallel RC4 Encryption Engine
K.H. Tsoi, K.H. Lee and P.H.W. Leong
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An FPGA Implementation of Triangle Mesh Decompression
T. Mitra, T. Chiush
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| Poster Session 1 |
| Paper Session 2 : Networking I
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Single-chip Gigabit Mixed-version IP Router on Virtex-II Pro
G. Brebner
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Control and Configuration Software for a Reconfigurable Networking Hardware Platform
T. Sproull, J. Lockwood, D. Taylor
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| Paper Session 3 : Tools I
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Peer-to-peer Hardware-software Interfaces for Reconfigurable Fabrics
M. Mishra and S. Goldstein
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PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
O. Mencer
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Coarse-Grain Pipelining for Multiple FPGA Architectures
Heidi Ziegler, Mary Hall, Joonseok Park, Pedro Diniz and Byoungro So
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| Poster Session 2 |
| Paper Session 4 : Template Matching
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FPGA-based Template Matching using Distance Transforms
S. Hezel, A. Kugel, R. Manner and D. Gavrila
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Reconfigurable Shape-Adaptive Template Matching Architectures
J. Gause, P.Y.K. Cheung, W. Luk
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| Tuesday, April 23, 2002 |
| Paper Session 5 : Networking II
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Assisting Network Intrusion Detection with Reconfigurable Hardware
R. Franklin, D. Carver and B. Hutchings
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GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing
P. Bellos, J. Flidr, T. Lehman, B. Schott and K. Underwood
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Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic
G. Memik, S. Memik and W. Mangione-Smith
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| Poster Session 3 |
| Paper Session 6 : Architecture I
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Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
G. Stitt, B. Grattan and F. Vahid
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Queue Machines: Hardware Compilation in Hardware
H. Schmit, B. Levine and B. Ylvisaker
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| Paper Session 7 : Applications II
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Custom Computing Machines for the Set Covering Problem
C. Plessl and M. Platzner
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Using Floating Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations
G. Lienhart, A. Kugel and R. Manner
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Analysis and Implementation of the Discrete Element Method using a Dedicated Highly Parallel Architecture in Reconfigurable Computing
B.C. Schaffer, S.F. Quigley and A.H.C. Chan
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| Poster Session 4 |
| Paper Session 8 : Architecture II
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Mobile Memory: Improving memory locality in very large reconfigurable fabrics
Rong Yan and Seth Goldstein
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Hardware-Assisted Fast Routing
A. DeHon, R. Huang, J. Wawrzynek
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| Wednesday, April 23, 2002 |
| Paper Session 9 : Tools II
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Optimum Wordlength Allocation
G. Constantinides, P.Y.K. Cheung, W. Luk
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Precis: A Design-Time Precision Analysis Tool
M. Chang and S. Hauck
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Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems
D. Kulkami, W. Najjar, R. Rinker and F. Kurdahi
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| Poster Session 3 |
| Paper Session 10 : Image Compression
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Hyperspectral Image Compression on Reconfigurable Platforms
T. Fry, S. Hauck
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MPEG-compliant Entropy Decoding on FPGA-augmented TriMedia/CPU64
M. Sima, S. Cotofina, S. Vassiliadis, J. van Eijndhoven, K. Vissers
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