Home   Call for Papers  Important Dates  Committees  Related Conferences   Past FCCMs   Author Info Registration, Travel and Accommodation   Technical Program FCCM 2011: The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines Location: Salt Lake City, Utah Conference Dates: May 1-3, 2011 Final Program Also available in PDF Sunday, May 1, 2011 1:30pm          FCCM Workshop High-Level Synthesis and Parallel Computation Models Workshop organized by: Kyle Rupnow, Advanced Digital Sciences Center (ADSC), Singapore Satnam Singh, Microsoft Research, UK John Wawrzynek, UC Berkeley, USA Workshop Speakers: High-level Synthesis of Threaded Concurrency Deming Chen, UIUC (PDF) Mingjie Lin, University of Central Florida (PDF) New Directions in Parallel Computation Models Mary Hall, University of Utah (PDF) Carl Ebeling, University of Washington High Level Synthesis of Implicity Concurrency David Bacon, IBM Research (PDF) Hugo Andrade, Nataional Instruments (PDF) 6:00pm          Wecome Reception Monday, May 2, 2011   8:00am          Registration Opens   8:30am          Opening Remarks   8:45am          Monday morning, Session 1:  Reconfigurable Computing   A Sparse Matrix Personality for the Convey HC-1 Krishna K. Nagar and Jason D. Bakos University of South Carolina   Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification Lingkan Gong and Oliver Diessel University of New South Wales   Mixed Precision Processing in Reconfigurable Systems 1Gary C.T. Chow, 1K.W. Kwok, 1Wayne Luk and 2Philip Leong 1Imperial College London, 2The University of Sydney   Dynamic Communication in a Coarse Grained Reconfigurable Array (short) Robin Panda and Scott Hauck University of Washington   Run-Time Resource Allocation for Simultaneous Multi-Tasking in Multi-Core Reconfigurable Processors (short) Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel and Juergen Becker Karlsruhe Institute of Technology (KIT)   An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs  (short) Jainik Kathiara and Miriam Leeser Northeastern University   Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA Board (short) 1Zheng Ding, 2Feng Zhao, 1Tinghui Wang, 1Wei Shu and 1Min-You Wu 1Shanghai Jiao Tong University, 2Digilent Electronic Technology Co. Ltd.   10:15am        Poster Session I   11:15am        Monday morning, Session 2: Comparing Implementations of Applications on Different Architectures   An FPGA implementation of Information Theoretic Visual-Saliency System and Its Optimization Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin and N. Vijaykrishnan Pennsylvania State University   Scalable, High Performance Fourier Domain Optical Coherence Tomography: why FPGAs and not GPGPUs Jian Li, Marinko Sarunic and Lesley Shannon Simon Fraser University   Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic Matina Lakka, Grigorios Chrysos, Ioannis Papaefstathiou and Apostolos Dollas Technical University of Crete   Implementation and Performance Analysis of Seal Encryption on FPGA, GPU, and Multicore Processors (short) Kostas Theoharoulis, Haralambos Antoniadis, Nikolaos Bellas and Christos Antonopoulos University of Thessaly   12:25pm        Lunch   2:00pm          Monday afternoon, Session 3: Applications I   Open Source FPGA Communications Framework (short) Peter Lieber and Brad Hutchings Brigham Young University   Efficient Calculation of Pairwise Nonbonded Forces (short) Matt Chiu, Md. Ashfaquzzaman Khan and Martin Herbordt Boston University   High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search (short) 1Yi-Hua E. Yang, 2Oguzhan Erdem and 1Viktor K. Prasanna 1University of Southern California, 2Middle-East Technical University   A Scalable Multi-FPGA Platform for Complex Networking Applications  (short) 1Sascha Mühlbach and 2Andreas Koch 1Center for Advanced Security Research Darmstadt, 2Technische  Universität Darmstadt   An FPGA-based Optical IOH Architecture for Embedded System (short) Ling Liu, Jincan Zhuang, Qianying Zhu, Shunyu Zhu, Zhiyuan Zhang, Xinxin Zhang, Lu Cao, Zhihong Yu, Xiangbin Wu and Dong Liu Intel   On Comparing Financial Price Solvers on FPGA (short) Qiwei Jin, David Thomas and Wayne Luk Imperial College London   Low-latency FPGA Based Financial Data Feed Handler (short) 1Robin Pottathuparambil, 2Jack Coyne, 2Jeffrey Allred, 2 William Lynch and 2Vincent Natoli 1University of North Carolina at Charlotte, 2Stone Ridge Technology   Design and Implementation of an FPGA-based Real-Time Face Recognition System (short) Janarbek Matai, Ali Irturk and Ryan Kastner University of California, San Diego   FPGA-Based Solid-State Drive Prototyping with NAND Flash Memories (short) 1Yu Cai, 2Eric F. Haratsch, 1Mark McCartney and 1Ken Mai 1Carnegie Mellon University, 2LSI Corporation   Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner using FPGA Devices and a High Level Synthesis Tool (short) 1Zhong-Ho Chen, 1Alvin Su, 2Scott Hauck and 2Ming-Ting Sun 1National Cheng-Kung University, 2University of Washington   SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing (short) Kunjan Patel, Chris Bleakley and Seamas McGettrick University College Dublin   109   A high-throughput, streaming, lossless data compression algorithm and its efficient hardware implementation Bharat Sukhwani, Bulent Abali, Bernard Brezzo and Sameh Asaad IBM T. J. Watson Research Center   3:00pm          Poster Session II   4:00pm          Monday afternoon, Session 4: Tools   HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping (Audience Choice Best Presentation Award FCCM 2011) Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson and Brad Hutchings Brigham Young University   Automatic HDL-based generation of homogeneous hard macros for FPGAs 1Sebastian Korf, 1Dario Cozzi, 1Markus Koester, 1Jens Hagemeyer, 1Mario Porrmann, 2Marco Domenico Santambrogio and 3Ulrich Rückert 1University of Paderborn, Germany, 2Massachusetts Institute of Technology, USA, 3University of Bielefeld, Germany   Using Functional Programming to Generate an LDPC Forward Error Corrector Andy Gill, Tristan Bull, Dan DePardo, Andrew Farmer, Ed Komp and Erik Perrins University of Kansas   6:30pm          Demo Night     Tuesday, May 3, 2011   8:00am          Registration Opens   8:30am          Tuesday morning, Session 5: Reconfigurable Computing in the Data Center (Panel Session)   Reconfigurable Data Processing for Clouds (short) 1Anil Madhavapeddy and 2Satnam Singh 1University of Cambridge, 2Microsoft Research Cambridge, UK   10:00am        Coffee Break   10:30am        Tuesday morning, Session 6: Architecture and Systems   TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System 1Nehir Sonmez, 1Oriol Arcas, 1Otto Pflucker, 1Osman Unsal, 1Adrián Cristal, 1Ibrahim Hur, 2Satnam Singh and 1Mateo Valero 1Barcelona Supercomputing Center, 2Microsoft Research Cambridge, UK   The PowerPC 405 Memory Sentinel and Injection System Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao and Matthew French USC/ISI   Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs Andrew Schmidt, Bin Huang, Ron Sass and Matt French University of North Carolina at Charlotte, Information Sciences Institute University of Southern California   FUSE: Front-end user framework for OS abstraction of hardware accelerators Aws Ismail and Lesley Shannon Simon Fraser University   11:50am        Lunch   1:20pm          Tuesday afternoon, Session 7: High-Level Synthesis and Tools   Multilevel Granularity Parallelism Synthesis on FPGAs  (Best Paper Award FCCM 2011) 1Alexandros Papakonstantinou, 2Yun Liang, 1John Stratton, 3Karthik Gururaj, 1Deming Chen, 1Wen-Mei Hwu and 3Jason Cong 1University of Illinois, Urbana Champaign, 2Advance Digital Science Center, Illinois at Singapore, 3University of California, Los Angeles   Synthesis of Platform Architectures from OpenCL Programs Muhsen Owaida, Nikolaos Bellas, Konstantis Daloukas and Christos Antonopoulos University of Thessaly   Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi 1Zain ul-Abdin, 2Anders Ahlander and 1Bertil Svensson 1Halmstad University, 2SAAB AB   Towards Synthesis-Free JIT Compilation to Commodity FPGAs (short) Davor Capalija and Tarek Abdelrahman University of Toronto   Automated Placement for Parallelized FPGA FFTs (short) 1Suraj Gowda, 2Aaron Parsons, 3Robert Jarnot and 4Dan Werthimer 1UC Berkeley, EECS, 2UC Berkeley, Astronomy, 3Jet Propulsion Laboratory, California Institute of Technology, 4UC Berkeley Space Sciences Laboratory   Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems (short) 1Manish Arora, 1Jack Sampson, 1Nathan Goulding-Hotta, 2Jonathan Babb, 1Ganesh Venkatesh, 1Michael Taylor and 1Steven Swanson 1University of California, San Diego, 2Massachusetts Institute of Technology   Extending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level Synthesis (short) Rohit Sinha and Hiren Patel University of Waterloo   2:40pm          Poster Session III   3:40pm          Tuesday afternoon, Session 8: Applications II   String Matching in Hardware using the FM index Edward Bryann Fernandez, Walid Najjar and Stefano Lonardi University of California Riverside   Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs Nikolaos Alachiotis, Simon Berger and Alexandros Stamatakis Heidelberg Institute for Theoretical Studies   Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth Kentaro Sano, Yoshiaki Hatsuda and Satoru Yamamoto Tohoku University   Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression Hoang Le, Weirong Jiang and Viktor Prasanna USC   5:00pm          Awards and Summary   5:15pm         Conference Ends