{"id":3503,"date":"2024-04-08T05:44:20","date_gmt":"2024-04-08T05:44:20","guid":{"rendered":"https:\/\/www.wp.fccm.org\/?page_id=3503"},"modified":"2024-04-23T06:13:11","modified_gmt":"2024-04-23T06:13:11","slug":"posters-2024","status":"publish","type":"page","link":"https:\/\/www.wp.fccm.org\/posters-2024\/","title":{"rendered":"Posters 2024"},"content":{"rendered":"\n

FCCM 2024 Posters<\/h1>\n\n\n\n

Session A <\/h2>\n\n\n\n
Title<\/th>Authors<\/th><\/tr><\/thead>
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS <\/td>Gabriele Montanaro, Andrea Galimberti, Davide Zoni (Politecnico di Milano)<\/td><\/tr>
Good Enough Is Perfect:Lowering the Barrier to VTR Interoperability with Error Resilient Cluster Reconstruction <\/td>Kate Thurmer, Mohamed A. Elgammal, Vaughn Betz (University of Toronto)<\/td><\/tr>
A Near-Sensor Image Processing Accelerator for Low-end FPGA Design<\/td>Peter Mbua, Zhaoqi Wang, Maximillian Panoff, Christophe Bobda (University of Florida)<\/td><\/tr>
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap<\/td>Martin Langhammer (Intel Corporation); George A. Constantinides (Imperial College London, UK)<\/td><\/tr>
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs<\/td>Benjamin Reynolds, Shahzad Ahmad Butt, Pohrong Rita Chu, Veeraraghavan Ramamurthy, Xiao Xiao, Setareh Sharifian, Sergey Gribok, Bogdan Pasca (Intel Corporation)<\/td><\/tr>
Improving The Routing Performance of VTR 8 Under Resource Constraints<\/td>Junjie Hou (Huawei & Shanghai Jiao Tong University); Yue Zha, Jianjiang Zeng (Huawei); Jianguo Yao (Shanghai Jiao Tong University)<\/td><\/tr>
Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision<\/td>Xilai Dai, Yuzong Chen, Mohamed Abdelfattah (Cornell University)<\/td><\/tr>
SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design<\/td>Hao Zhou, Yang Liu, Hongji Wang (Fudan University); Enhao Tang, Shun Li (Fuzhou Universiity); Yifan Zhang (Fudan University); Kun Wang (Fudan university)<\/td><\/tr>
Learned Index Acceleration with FPGAs: A SMART Approach<\/td>geetesh more (University of New brunswick); Suprio Ray (University of New Brunswick, Fredericton); Kenneth B. Kent (University of New Brunswick)<\/td><\/tr>
SpGCN: A FPGA based graph convolutional network accelerator for sparse graphs<\/td>Xiangzhi Xu, Qi Liu, Wenjin Huang, WenLu Peng, Yihua Huang (Sun Yat-sen University)<\/td><\/tr>
FlexFlow: A Programming Abstraction for Flexible Dataflow Support on Reconfigurable Accelerators<\/td>Shaojie Xiang, Niansong Zhang, Hongzheng Chen (Cornell University); Haiyu Wang (Peking University); Zhiru Zhang (Cornell University)<\/td><\/tr>
HBMorphic: Fully Homomorphic Encryption Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA<\/td>Hassan Nassar (KIT); Lars Bauer, J\u221a\u2202rg Henkel (Karlsruhe Institute of Technology)<\/td><\/tr>
Resource and Phase Awareness for Dynamically Scheduled High-Level Synthesis<\/td>Mathias Bouilloud (Imperial College London); Lana Josipovic (ETH Zurich); Wayne Luk (Imperial College London)<\/td><\/tr>
Energy-Aware Synchronization of Hardware Tasks in Multi-Tenant Systems<\/td>Cornelia Wulf, G\u221a\u2202khan Akg\u221a\u00ban (TU Dresden); Mehdi Safarpour (University of Oulu); Anastacia Grishchenko, Diana G\u221a\u2202hringer (TU Dresden)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Session B <\/h2>\n\n\n\n
Title<\/th>Authors<\/th><\/tr><\/thead>
OS4C: An Open-Source SR-IOV System for SmartNIC-based Cloud Platforms<\/td>Scott Smith, Yuan Ma, Marissa Lanz Kate, Bill Dai (University of Illinois Urbana-Champaign); Martin Ohmacht, Bharat Sukhwani, Hubertus Franke (IBM Research); Volodymyr Kindratenko (University of Illinois at Urbana-Champaign); Deming Chen (University of Illinois, Urbana-Champaign)<\/td><\/tr>
Variable Bit-width Random Number Generation for Implementing Direct Simulation Monte Carlo on Field-Programmable Gate Arrays<\/td>Saleen Bhattarai, Andrew Lambert, David Petty (The University of New South Wales Canberra); Sean O’Byrne (The Australian National University)<\/td><\/tr>
High-Performance Reconfigurable Accelerator for Knowledge Graph Reasoning<\/td>Hanning Chen, Ali Zakeri, Yang Ni (University of California, Irvine); Fei Wen (Texas A&M University); Behnam Khaleghi (University of California San Diego); Hugo Latapie (Cisco Systems); Mohsen Imani (University of California Irvine)<\/td><\/tr>
BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators<\/td>Yuhao Liu, Salim Ullah, Akash Kumar (Chair of Processor Design, TU Dresden)<\/td><\/tr>
RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA<\/td>Huawen Liang, Qizhe Wu, Wei Yuan, Teng Tian, Xi Jin (University of Science and Technology of China)<\/td><\/tr>
Stay Flexible: FPGA Acceleration of Graph Neural Networks on a High-Performance NPU Overlay<\/td>Taikun Zhang, Andrew Boutros (University of Toronto); Sergey Gribok, Kwadwo Boateng (Intel Corp.); Vaughn Betz (University of Toronto)<\/td><\/tr>
AXI SmartDisconnect: Guiding Memory Performance in Multi-Tenant FPGAs<\/td>Kristiyan Manev (EnduroSat)<\/td><\/tr>
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators<\/td>MD Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks (University of Arkansas); Joel Mandebi (Advanced Micro Devices, Inc. (AMD)); Jason Bakos (University of South Carolina); Miaoqing Huang, David Andrews (University of Arkansas)<\/td><\/tr>
Best of Both Worlds: Integrating Scalable Analytical Placement into the Flexible VTR Framework<\/td>Rachel Selina Rajarathnam (University of Texas at Austin, Austin, TX, USA); Kate Thurmer, Vaughn Betz (University of Toronto, Toronto, ON, Canada); Mahesh A. Iyer (Intel Corporation, San Jose, CA, USA); David Z. Pan (University of Texas at Austin, Austin, TX, USA)<\/td><\/tr>
Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes<\/td>Stephanie Soldavini (Politecnico di Milano); Felix Suchert (TU Dresden); Serena Curzel, Michele Fiorito (Politecnico di Milano); Karl Friedrich Alexander Friebel (TU Dresden); Fabrizio Ferrandi (Politecnico di Milano); Radim Cmar (Sygic); Jeronimo Castrillon (TU Dresden); Christian Pilato (Politecnico di Milano)<\/td><\/tr>
Efficient profiling of HLS code<\/td>Kimberley Stonehouse, Jose Lopes, Benoit Pradelle (AMD)<\/td><\/tr>
Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA<\/td>Kejia Shi, Manting Zhang, Keqing Zhao, Xiaoxing Wu, Jun Yu, Kun Wang (Fudan University)<\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"

FCCM 2024 Posters Session A Title Authors A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS Gabriele Montanaro, Andrea Galimberti, Davide Zoni (Politecnico di Milano) Good Enough Is Perfect:Lowering the Barrier to VTR Interoperability with Error Resilient Cluster Reconstruction Kate Thurmer, Mohamed A. Elgammal, Vaughn Betz (University of Toronto) A Near-Sensor Image Processing … <\/p>\n

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