{"id":2683,"date":"2022-05-03T03:40:59","date_gmt":"2022-05-03T03:40:59","guid":{"rendered":"https:\/\/www.wp.fccm.org\/?page_id=2683"},"modified":"2023-05-07T18:31:22","modified_gmt":"2023-05-07T18:31:22","slug":"posters-2023","status":"publish","type":"page","link":"https:\/\/www.wp.fccm.org\/posters-2023\/","title":{"rendered":"FCCM 2023 Posters and PhD Forum"},"content":{"rendered":"\n

Session A — Virtual Posters<\/h2>\n\n\n\n
Title<\/th>Authors<\/th><\/tr><\/thead>
CAKS-NMC: Compiler-Assisted Automatic Kernel Selection for FPGA-based Near-Memory Computing Platforms<\/td>V. Iskandar; A. Hantriono; M. Ghany; D. Goehringer<\/td><\/tr>
Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks<\/td>Y. Bai; H. Zhou; K. Zhao; J. Chen; J. Yu; K. Wang<\/td><\/tr>
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for Energy Efficient Hardware Acceleration of Image Processing and Machine Learning applications<\/td>Z. Aizaz; K. Khare; A. Tirmizi<\/td><\/tr>
OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference<\/td>S. Gandham; L. Yin; H. Zheng; M. Lin<\/td><\/tr>
An Efficient Piecewise Linear Approximation of Non-linear Operations for Transformer Inference<\/td>H. Lu; Q. Mei; K. Wang<\/td><\/tr>
SpCNA: An FPGA-based Accelerator for Point Cloud Convolutional Neural Networks<\/td>G. Zhou; K. Guo; X. Chen; K. LEUNG<\/td><\/tr>
MSBF-LSTM: Most-significant Bit-first LSTM Accelerators with Energy Efficiency Optimisations<\/td>S. Bian; H. Li; C. Wang; C. Song; Y. Tang<\/td><\/tr>
Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA<\/td>Y. Wang; Y. Li; H. Zhang; J. Yu; K. Wang<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Session B — In-person Posters<\/h2>\n\n\n\n
Title<\/th>Authors<\/th><\/tr><\/thead>
Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis<\/td>T. Havinga; X. Jiao; W. Liu; I. Moerman<\/td><\/tr>
Runtime Memory Disambiguation for Hybrid-Scheduled High-Level Synthesis<\/td>R. Szafarczyk; S. Nabi; W. Vanderbauwhede<\/td><\/tr>
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors<\/td>Y. Gao; C. Keilbart; M. Chua; E. Matthews; S. Wilton; L. Shannon<\/td><\/tr>
Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs<\/td>F. Kono; N. Nakasato; M. Nakata<\/td><\/tr>
ReLoDAQ: Resource-Efficient, Low Overhead 200 Gbit\/s Data Acquisition System for 6G Prototyping<\/td>C. Karle; M. Neu; J. Pfau; J. Sperling; J. Becker<\/td><\/tr>
b8c: SpMV accelerator implementation leveraging high memory bandwidth<\/td>J. Oliver; C. \u00c1lvarez; T. Cervero; X. Martorell; J. Davis; E. Ayguad\u00e9<\/td><\/tr>
Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays<\/td>M. Kabir; J. Hollis; A. Panahi; J. Bakos; M. Huang; D. Andrews<\/td><\/tr>
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks<\/td>G. Yang; J. Lei; Z. Fang; Y. Li; J. Zhang; W. Xie<\/td><\/tr>
Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management<\/td>A. Filgueras; M. Vidal; D. Jim\u00e9nez-Gonz\u00e1lez; C. \u00c1lvarez; X. Martorell<\/td><\/tr>
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing<\/td>A. Drewes; V. Burtsev; B. Gurumurthy; M. Wilhelm; D. Broneske; G. Saake; T. Pionteck<\/td><\/tr>
Efficient implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGA<\/td>M. Heer; J. Quevedo; M. Abdelatti; R. Sendag; M. Sodhi<\/td><\/tr>
Decision Forest Training Accelerator Based on Binary Feature Decomposition<\/td>T. Van Chu; Y. Mizutani; Y. Nagahara; S. Kumazawa; K. Kawamura; J. Yu; M. Motomura<\/td><\/tr>
Accelerating Graph Analytics with oneAPI and Intel FPGAs<\/td>J. Bickerstaff; L. Kljucaric; A. George<\/td><\/tr>
FEASTS: Feature Extraction Accelerator for Streaming Time Series<\/td>P. Yuvaraj; A. Kalantar; E. Keogh; P. Brisk<\/td><\/tr>
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design<\/td>B. Peng; S. Sun; Y. Dai<\/td><\/tr>
Scalable Quantum Error Correction for Surface Codes using FPGA<\/td>N. Liyanage; Y. Wu; A. Deters; L. Zhong<\/td><\/tr>
Clustering Classification on FPGAs for Neuromorphic Feature Extraction<\/td>L. Kljucaric; D. George<\/td><\/tr>
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization<\/td>Y. Dai; Y. Qiu; Q. Zhu; J. Li; W. Yin; L. Wang<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Session C — PhD Forum<\/h2>\n\n\n\n
Title<\/th>Authors<\/th><\/tr><\/thead>
Reformulating the FPGA Routability Prediction Problem with Machine Learning<\/td>Andrew David Gunther, Steve Wilton (The Univ. of British Columbia)<\/td><\/tr>
Hardware\/Software Co-design for Machine Learning Accelerators<\/td>Hanqiu Chen, Cong (Callie) Hao (Georgia Institute of Technology)<\/td><\/tr>
From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level Synthesis<\/td>Rishov Sarkar, Cong (Callie) Hao (Georgia Institute of Technology)<\/td><\/tr>
Power Side-Channel Attacks and Defenses for Neural Network Accelerators<\/td>Vincent Meyers, Mehdi B. Tahoori (Karlsruhe Institute of Technology)<\/td><\/tr>
Enabling Elastic Resource Management in Cloud FPGAs via A Multi-layer Collaborative Approach<\/td>Wenbin Teng, Xuehai Zhou (University of Science and Technology of China)<\/td><\/tr>
A Framework for Graph Machine Learning on Heterogeneous Architecture<\/td>Yi-Chien Lin, Viktor Prasanna (University of Southern California, Los Angeles, California)<\/td><\/tr>
DataMaster: A GNN-based Data Type Optimizer for Dataflow Design in FPGA<\/td>Zheyuan Zou, Xuehai Zhou (University of Science and Technology of China)<\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"

Session A — Virtual Posters Title Authors CAKS-NMC: Compiler-Assisted Automatic Kernel Selection for FPGA-based Near-Memory Computing Platforms V. Iskandar; A. Hantriono; M. Ghany; D. Goehringer Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks Y. Bai; H. Zhou; K. Zhao; J. Chen; J. Yu; K. Wang FASBM: FPGA-specific Approximate Sum-based Booth multipliers for Energy Efficient Hardware … <\/p>\n

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