{"id":2477,"date":"2022-04-01T01:52:02","date_gmt":"2022-04-01T01:52:02","guid":{"rendered":"https:\/\/www.wp.fccm.org\/?page_id=2477"},"modified":"2023-10-24T01:05:59","modified_gmt":"2023-10-24T01:05:59","slug":"technical-program-2023","status":"publish","type":"page","link":"https:\/\/www.wp.fccm.org\/technical-program-2023\/","title":{"rendered":"Program 2023"},"content":{"rendered":"\n

FCCM 2023 Preliminary<\/strong> Program<\/strong><\/h1>\n\n\n\n

*All times shown in the Pacific Time Zone (UTC-8)<\/strong><\/p>\n\n\n\n

Monday (May 8) and Thursday (May 11): Workshops and Tutorials<\/a><\/strong><\/h2>\n\n\n\n

Tuesday – May 9<\/strong><\/h2>\n\n\n\n

\u2605<\/mark> indicates best paper candidate<\/em><\/p>\n\nOpen Research Objects (ORO) \"\"\nResearch Objects Reviewed (ROR) \"\"\nResults Reproduced (ROR-R) \"\"\n\n\n\n

\n\n\n\n
8:00 am – 8:45 am<\/td>Light Breakfast and Registration<\/td><\/tr>
8:45 am – 9:00 am<\/td>Opening<\/span><\/strong><\/td><\/tr>
9:00 am – 10:00 am<\/td>Keynote: The Programmable Imperative of Networking: Past and Future<\/mark><\/strong><\/a>
<\/strong><\/mark>Speaker: Mike Fitton, Intel <\/mark>

Chair: Viktor Prasanna<\/td><\/tr>
10:15 am – 11:30 am<\/td>Session 1 – High-Level Synthesis<\/mark><\/strong>
Chair: Ron Sass<\/td><\/tr>
<\/td>LightningSim: Fast and Accurate Trace-Based Simulation for High-Level Synthesis<\/strong> \u2605<\/mark> \"\" \"\" \"\"
Rishov Sarkar and Cong Hao (Georgia Institute of Technology)<\/td><\/tr>
<\/td>PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs<\/strong>
Moazin Khatti and Xingyu Tian (Simon Fraser University); Yuze Chi, Licheng Guo, and Jason Cong (UCLA); Zhenman Fang (Simon Fraser University)<\/td><\/tr>
<\/td>SCCL: An open-source SystemC to RTL translator<\/strong> \"\" \"\" \"\"
Zhuanhao Wu (University of Waterloo); Maya Gokhale (Lawrence Livermore National Laboratory); Scott Lloyd (Brigham Young University); Hiren Patel (University of Waterloo)<\/td><\/tr>
<\/td>Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs<\/strong> (short paper)
Xiaochen Hao (Peking University); Hongbo Rong (Intel Labs); Mingzhe Zhang (Tsinghua University); Ce Sun (University of Science and Technology of China); Zhuofu Tao (University of California, Los Angeles); Yu Zhang (University of Science and Technology of China); Lei He (University of California, Los Angeles); Eric Petit (Intel); Wenguang Chen (Tsinghua University); Yun Liang (Peking University)<\/td><\/tr>
11:30 am – 12:00 pm<\/td>Poster Session A<\/mark><\/strong><\/a> (virtual)<\/td><\/tr>
12:00 pm – 1:30 pm<\/td>Lunch<\/td><\/tr>
1:30 pm – 2:45 pm <\/td>Session 2 – Architecture and CAD<\/mark><\/strong>
Chair: Kia Bazargan<\/td><\/tr>
<\/td>Placement Optimization for NoC-Enhanced FPGAs<\/strong> \u2605<\/mark> \"\" \"\"
Srivatsan Srinivasan, Andrew Boutros, Fatemehsadat Mahmoudi, and Vaughn Betz (University of Toronto)<\/td><\/tr>
<\/td>BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs<\/strong> \"\" \"\" \"\"
Yuzong Chen and Mohamed Abdelfattah (Cornell University)<\/td><\/tr>
<\/td>A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems<\/strong> \u2605<\/span>
Andrew David Gunter and Steven Wilton (University of British Columbia)<\/td><\/tr>
<\/td>CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data Centers<\/strong> (short paper)
Chenjiu Wang (SKLP, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences); Ke He (unaffiliated); Ruiqi Fan (SKLP, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences); Xiaonan Wang (WUXI Institute of Interconnect Technology); Wei Wang (unaffiliated); Qinfen Hao (SKLP, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences)<\/td><\/tr>
2:45 pm – 3:00 pm <\/td>Break<\/td><\/tr>
3:00 pm – 4:15 pm<\/td>Session 3 – Applications\/ML<\/mark><\/strong>
Chair: Zhenman Fang<\/td><\/tr>
<\/td>Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-integer Geometric Programming<\/strong> \"\" \"\" \"\"
Yuhao Ding, Jiajun Wu, and Yizhao Gao (The University of Hong Kong); Maolin Wang (AI Chip Center for Emerging Smart Systems); Hayden So (The University of Hong Kong)<\/td><\/tr>
<\/td>MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources<\/strong> \"\" \"\" \"\"
Jiajun Wu, Jiajun Zhou, Yizhao Gao, Yuhao Ding, Ngai Wong, and Hayden So (The University of Hong Kong)<\/td><\/tr>
<\/td>Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures<\/strong>
Alireza Khataei, Gaurav Singh, and Kia Bazargan (University of Minnesota)<\/td><\/tr>
<\/td>Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform<\/strong> (short paper)
Pengzhou He, Tianyou Bao, Yazheng Tu, and Jiafeng Xie (Villanova University)<\/td><\/tr>
4:15 pm – 4:45 pm<\/td>Poster Session B<\/mark><\/a><\/strong> (in person)<\/td><\/tr>
4:45 pm – 6:00 pm<\/td>Break<\/td><\/tr>
6:00 pm – 9:00 pm<\/td>Reception<\/mark><\/strong> and Demo night<\/mark><\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Wednesday – May 10<\/strong><\/h2>\n\n\n\n
8:00 am – 8:45 am<\/td>Light Breakfast and Registration<\/td><\/tr>
9:00 am – 10:00 am<\/td>Keynote: Bitstream Design Abstraction to Build Reconfigurable Machines and Applications<\/mark><\/a><\/strong>
<\/strong><\/mark>Speaker: Prasanna Sundararajan
Principal Architect, Microsoft Azure<\/mark>

Chair: Wayne Luk, Imperial College London<\/td><\/tr>
10:15 am – 11:15 am<\/td>Panel: Large Language Model (LLM) inference on FPGAs, GPUs, etc.<\/span><\/strong><\/td><\/tr>
11:15 am – 11:30 am<\/td>Break<\/td><\/tr>
11:30 am – 12:00 pm<\/td>PhD Forum Posters<\/mark><\/a><\/strong> (in person)<\/td><\/tr>
12:00 pm – 1:30 pm<\/td>Lunch<\/td><\/tr>
1:30 pm – 2:45 pm<\/td>Session 4 – Applications\/ML<\/mark><\/strong>
Chair: Mohamed Abdelfattah<\/td><\/tr>
<\/td>ATHEENA: A Toolflow for Hardware Early-Exit Network Automation<\/strong> \u2605<\/mark> \"\" \"\" \"\"
Benjamin Biggs, George A. Constantinides, and Christos-Savvas Bouganis (Imperial College London, UK)<\/td><\/tr>
<\/td>Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs<\/strong>
Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, and Dinesh Gaitonde (AMD)<\/td><\/tr>
<\/td>HARFLOW3D: A latency-oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices<\/strong> \"\" \"\"
Petros Toupas (Imperial College London, Information Technologies Institute at CERTH); Alexander Montgomerie-Corcoran (Imperial College London); Dimitrios Tzovaras (Information Technologies Institute at CERTH); Christos-Savvas Bouganis (Imperial College London, UK)<\/td><\/tr>
<\/td>Power2Picture: Using Generative CNNs for Input Recovery of Neural Network Accelerators through Power Side-Channels on FPGAs<\/strong>
Lukas Huegle, Martin Gotthard, Vincent Meyers, Jonas Krautter, Dennis R. E. Gnad, and Mehdi B. Tahoori (Karlsruhe Institute of Technology (KIT))<\/td><\/tr>
2:45 pm – 3:00 pm <\/td>Break<\/span><\/td><\/tr>
3:00 pm – 4:15 pm<\/td>Session 5 – Applications<\/mark><\/strong>
Chair: Gabriel Weisz<\/td><\/tr>
<\/td>Computing and Compressing Electron Repulsion Integrals on FPGAs<\/strong>
Xin Wu, Tobias Kenter, Robert Schade, Thomas D. K\u00fchne, and Christian Plessl (Paderborn University)<\/td><\/tr>
<\/td>Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform<\/strong>
Yuying ZHANG, Sathi Sarveswara Reddy, and Zili KOU (Hong Kong University of Science and Technology); Sharad Sinha (Indian Institute of Technology Goa); Wei ZHANG (Hong Kong University of Science and Technology)<\/td><\/tr>
<\/td>SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms<\/strong>
Alec Lu and Zhenman Fang (Simon Fraser University)<\/td><\/tr>
<\/td>DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference<\/strong> (short paper)
Hanqiu Chen and Cong Hao (Georgia Institute of Technology)<\/td><\/tr>
4:15 pm – 4:30 pm<\/td>Closing and Award Ceremony <\/span><\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

FCCM 2023 Preliminary Program *All times shown in the Pacific Time Zone (UTC-8) Monday (May 8) and Thursday (May 11): Workshops and Tutorials Tuesday – May 9 \u2605 indicates best paper candidate Open Research Objects (ORO) Research Objects Reviewed (ROR) Results Reproduced (ROR-R) 8:00 am – 8:45 am Light Breakfast and Registration 8:45 am – … <\/p>\n

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