Tentative Workshop and Tutorial Schedule
05/04/2025, Sunday
| Date | Time | Name | Organizer |
| 5/4/2025 | 1 PM-4 PM | Hardware/Software Codesign for Big Data Acceleration | Zhenman Fang (Simon Frasier University) |
| 5/4/2025 | 1 PM-4:30 PM | Next-Generation Adaptable Computing for Omics | Peipei Zhou (Brown University), Madhura Purnaprajna (AMD) |
| 5/4/2025 | 6:00 PM to 7:15 PM | Sunday Panel Discussion: The Future of FCCMs Beyond Mooreâs Law | Jason Bakos (University of South Carolina) |
05/07/2025, Wednesday
| Date | Time | Name | Organizer |
| 5/7/2025 | 9:00 AM to 5:00 PM | Open Cloud Testbed Tutorial and User Workshop | Miriam Leeser (Northeastern University) |
| 5/7/2025 | 9:00 AM to 5:00 PM | Workshop on Mixed Analog-Digital Configurable Adaptable Processing (MADCAP) | Ramtin Zand (University of South Carolina) |
| 5/7/2025 | 9:00 AM to 12:00 PM | Tutorial: âARIES: Agile Programming on AI Engines in Python Interface and MLIR-based Compilation” | Peipei Zhou, Jinming Zhuang, Zhuoping Yang (Brown University) |
| 5/7/2025 | 1:30 PM to 2:30 PM | Tutorial: Incorporating CVA5, a Highly Configurable RISC-V Soft Processor, into Your FPGA Designs | Lesley Shannon, Chris Keilbart, Mohammad Shahidzadeh (Simon Frasier University) |
Sunday, May 4
1:00 to 4:00: Workshop: âHardware/Software Codesign for Big Data Accelerationâ, Chair: Zhenman Fang, Simon Frasier University
1:00 to 4:30: Workshop: âNext-Generation Adaptable Computing for Omicsâ Chairs: Peipei Zhou and Madhura Purnaprajna, Brown University
Unlock the Future of Omics with Adaptable Computing!
The field of omics is generating data at an unprecedented scale, pushing the boundaries of computational performance. Join us at FCCMâ25 for the Next-Generation Adaptable Computing for Omics workshop, where industry and academic leaders will explore cutting-edge FPGA, CGRA, and dataflow architectures tailored for genomics, proteomics, and beyond. Through insightful talks and expert panel discussions, weâll dive into how these adaptable architectures can revolutionize healthcare, biotechnology, and environmental research. Whether you’re a researcher, developer, or hardware enthusiast, this workshop is your gateway to shaping the future of computational genomics. Donât miss this opportunity to engage, learn, and innovate!
6:00 to 7:15: Panel: âSunday Panel Discussion: The Future of FCCMs Beyond Mooreâs Lawâ, Chair: David Andrews, University of Arkansas
For decades, the steady march of Mooreâs Law has driven unprecedented advancements in computing power. But as transistor scaling slows and the end of Dennard scaling looms, the industry faces a critical inflection point. What comes next? Join us for an engaging panel discussion where leading experts will explore the evolution of todayâs FPGA-based computing architectures into the post-Mooreâs Law era. With AI workloads dominating and emerging technologies reshaping the landscape, weâll discuss:
– The future of CMOS-based reconfigurable computing fabrics
– The potential rise of mixed-signal digital/analog custom machines
– The research directions that will define the next wave of computing innovation
If youâre curious about the next frontier in computing and how we navigate the transition beyond traditional transistor scaling, this is a discussion you wonât want to miss!
Wednesday, May 7
9:00 to 5:00: Tutorial: âOpen Cloud Testbed Tutorial and User Workshopâ Chair: Miriam Leeser, Northeastern University
(coffee breaks: 10:00 to 10:30 and 2:00 to 2:30, lunch: 12:00 to 1:00)
Supercharge Your Research with the Open Cloud Testbed!
Join us for a full-day Open Cloud Testbed (OCT) Tutorial and User Workshop at FCCM 2025 and gain hands-on experience with cutting-edge FPGA-enhanced cloud computing! OCT, an NSF-funded testbed, offers researchers access to high-performance, network-attached FPGAs, enabling groundbreaking discoveries in machine learning, networking, and reconfigurable computing. This tutorial will walk you through the full OCT workflowâfrom account setup to deploying FPGA-accelerated applicationsâall while engaging with expert users and real-world research case studies. Whether you’re new to FPGA cloud computing or an experienced researcher looking to push the boundaries of innovation, this workshop is your gateway to harnessing the power of OCT. Donât miss outâbe part of this dynamic research community!
9:00 to 5:00: Workshop: âWorkshop on Mixed Analog-Digital Configurable Adaptable Processing (MADCAP)â, Chair: Ramtin Zand, University of South Carolina
(coffee breaks: 10:00 to 10:30 and 2:00 to 2:30, lunch: 12:00 to 1:00)
The Workshop on Mixed Analog-Digital Configurable Adaptable Processing (MADCAP) at FCCM 2025 brings together leading minds from the FCCM and VLSI communities for a full day of collaboration and innovation. Mixed analog-digital Processing-in-Memory (PIM) and Computing-in-Memory (CIM) technologies promise groundbreaking efficiency gainsâreaching up to 1000 TOPs/Watt for small-scale matrix multiplication. But unlocking their full potential requires new integration strategies with FPGAs and FPGA-like SoCs, optimizing heterogeneous accelerator architectures for next-generation workloads.
MADCAP special sessions:
- âSMART: Sensor-centric Modular Architectures for Resilient Technology in IoTâ Chair: Arman Roohi, University of Illinois Chicago
- âIntegrating In-Memory Computing with FPGAs: Challenges and Emerging Opportunitiesâ, Chair: Luca Buonanno, HP Enterprise
- âEfficient Domain-Specific In-Memory Computing Acceleratorsâ Chair: Shaahin Angizi, New Jersey Institute of Technology
9:30 to 12:00: Tutorial: âARIES: Agile Programming on AI Engines in Python Interface and MLIR-based Compilationâ, Chair: Peipei Zhou, Jinming Zhuang, Zhuoping Yang, Brown University
Get ready to revolutionize your approach to AI accelerator design with ARIES: Agile Programming on AI Engines via Python Interface and MLIR-based Compilation! This hands-on tutorial at FCCMâ25 will introduce a powerful, Python-based programming model that simplifies AI Engine (AIE) development on AMDâs cutting-edge heterogeneous architectures. Learn how to leverage ARIES’ intuitive APIs, optimize AI accelerators with its MLIR-based compilation flow, and get practical experience building complex, high-performance designsâall while working directly with real hardware! Whether you’re a researcher, developer, or enthusiast in reconfigurable computing, this tutorial will empower you with the tools to streamline AI hardware development and push performance boundaries. Donât miss this opportunity to dive into the future of AI acceleration!
1:30 to 2:30: Tutorial: âIncorporating CVA5, a Highly Configurable RISC-V Soft Processor, into Your FPGA Designsâ, Chairs: Lesley Shannon, Chris Keilbart, Mohammad Shahidzadeh, Simon Frasier University
Unlock the Power of RISC-V with CVA5 on FPGA!
Join us for an exciting hands-on tutorial on CVA5, a highly configurable soft processor based on the open-source RISC-V architecture. Whether you’re an FPGA developer, hardware researcher, educator, or embedded systems enthusiast, this session will equip you with the skills to design, customize, and deploy your own RISC-V-based SoCs. Learn about CVA5âs architecture, optimized for FPGA architectures including AMD and Altera. Explore its unique configurability, and witness a live demo of Linux running on RISC-V on an FPGA. Don’t miss this opportunity to dive into cutting-edge processor design and take your FPGA development to the next level!