Poster Session 1
| ID | Title | Authors |
|---|---|---|
| 2 | Defending Side-Channel Attacks in Convolutional Neural Networks with Channel-Level Parallelization | YanKun Zhu, Ranxi Lin, Pingqiang Zhou (ShanghaiTech University) |
| 26 | TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs | Shuyang Li (Fudan University); Hanqing Zhang (Zhejiang University); Ruiqi Chen, Bruno da Silva (Vrije Universiteit Brussel); Giorgian Borca-Tasciuc (Rensselaer Polytechnic Institute); Dantong Yu (New Jersey Institute of Technology); Cong Hao (Georgia Institute of Technology) |
| 29 | SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networks | Binglei Lou, Ruilin Wu, Philip Leong (The University of Sydney) |
| 40 | Unlocking the AMD Neural Processing Unit for ML Training on the Client Using Bare-Metal-Programming Tools | André Rösti, Michael Franz (University of California, Irvine) |
| 48 | An Energy-Efficient FPGA-Based Vision Transformer Accelerator via Software-Hardware Co-Design | Jiacheng Cao, Jiaqi Guo, Wei Xiong, Huanlin Luo, Jian Wang, Jinmei Lai (Fudan University) |
| 90 | C2OPU: Hybrid Compute-in-Memory and Coarse-Grained Reconfigurable Architecture for Overlay Processing of Transformers | Siyuan Miao (University of California, Los Angeles); Lingkang Zhu (University of Nottingham, Ningbo, China); Chen Wu (Zhejiang Chiplet Engineering Research Center, Ningbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China); Shaoqiang Lu (Eastern Institute of Technology, Ningbo, China); Ting-Jung Lin (Zhejiang Chiplet Engineering Research Center, Ningbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China); Lei He (University of California, Los Angeles) |
| 110 | UltraFormer: Efficient Transformer Acceleration for and by FPGAs | Victor Agostinelli (Oregon State University, Pacific Northwest National Laboratory); Nicolas Bohm Agostini (Northeastern University); Antonino Tumeo (Pacific Northwest National Laboratory) |
| 115 | Microscaling Vision Transformers on FPGAs | Can Xiao (Imperial College London); Jianyi Cheng (University of Edinburgh); Aaron Zhao (Imperial College London) |
| 201 | BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs | Yuhao Liu (TU Dresden & ScaDS.AI); Salim Ullah (Ruhr-University Bochum); Akash Kumar (Ruhr-University Bochum &ScaDS.AI) |
| 233 | ITERA-LLM: Boosting Sub-8-Bit Large Language Model Inference Through Iterative Tensor Decomposition | Yinting Huang, Keran Zheng, Zhewen Yu, Christos-Savvas Bouganis (Imperial College London) |
Poster Session 2
| ID | Title | Authors |
|---|---|---|
| 54 | RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism | Wanzheng Weng, Pingqiang Zhou (ShanghaiTech University) |
| 62 | A High-Throughput Implementation of the MUSIC Algorithm Using AMD Versal AI Engine | Peifang Zhou (Fidus Systems Inc.) |
| 78 | APR-OIS: A Near-sensor Point Cloud Pre-processing Accelerator on FPGA | Yiming Gao, Herman Lam (University of FLorida) |
| 128 | Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms | Ehsan Kabir (University of Arkansas); Austin Downey, Jason D. Bakos (University of South Carolina); David Andrews, Miaoqing Huang (University of Arkansas) |
| 130 | On improving the HLS compatibility of large C/C++ code regions | Tiago Santos, João Bispo, João M. P. Cardoso (Faculty of Engineering, University of Porto); James C. Hoe (MangoBoost and Carnegie Mellon University) |
| 185 | Accelerating Scientific Model Optimization with a Pipelined FPGA-Based Differential Evolution Engine | Manuel de Castro (Universidad de Valladolid); Roberto R. Osorio (Universidade da Coruña); Yuri Torres (University of Valladolid); Diego R. Llanos (Universidad de Valladolid) |
| 193 | Optimizing Event Camera Performance: FPGA-Based Architectural Enhancements for Low-Light Conditions | Zhaoqi Wang, Peter Mbua, Christophe Bobda (University of Florida) |
| 238 | RV-ESMC: Efficient Sparse Matrix Convolution Processor based on RISC-V Custom instructions for Edge Platforms | Huachen Zhang, Bowen Jiang, Jianyang Ding, Tianshuo Lu, Zhilei Chai, Wei Xu (Jiangnan University) |
| 268 | EVO-QNN: Efficient Mixed-Precision Quantization Inference on RISC-V-Based Edge Device | Tianshuo Lu, Huachen Zhang, Jianyang Ding, Bowen Jiang, Zhilei Chai, Wei Xu (Jiangnan University) |
| 293 | DRSA: Accelerating Macro Placement on Commercial FPGAs | Menzo Bouaïssi, Paolo Ienne (EPFL); Lana Josipovic (ETH Zurich); Andrea Guerrieri (HES-SO and EPFL) |
Poster Session 3
| ID | Title | Authors |
|---|---|---|
| 75 | Low-Latency FFT/iFFT RTL Implementation for the FALCON Post-Quantum Signature Algorithm | Alexandre Ortega, Lilian Bossuet, Brice Colombier (Laboratoire Hubert Curien, Saint-Etienne, France) |
| 106 | Breaking New Ground: Division Directly in Memory | Farzad Razi (University of Minnesota); Mehran Shoushtari Moghadam, M. Hassan Najafi (Case Western Reserve University); Sercan Aygun (University of Louisiana at Lafayette); Marc Riedel (University of Minnesota) |
| 140 | Analog In-memory Computing Enhanced FPGA for High-Throughput and Energy-Efficient Acceleration | Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Xia Sheng, Giacomo Pedretti, Paolo Faraboschi, Jim Ignowski (Artificial Intelligence Research Lab (AIRL), Hewlett Packard Labs); Aman Arora (Arizona State University); Luca Buonanno (Artificial Intelligence Research Lab (AIRL), Hewlett Packard Labs) |
| 203 | BCIM: A Bit-Serial Approach for Block-Cipher-In-Memory | Andrew Dervay, Omar Al Kailani, Wenfeng Zhao (Binghamton University) |
| 237 | LLM-IMC: Automating Analog In-Memory Computing Architecture Generation with Large Language Models | Deepak Vungarala (New Jersey Institute of Technology); Md Hasibul Amin (University of South Carolina); Pietro Mercati (Intel Labs); Arman Roohi (University of Illinois Chicago); Ramtin Zand (University of South Carolina); Shaahin Angizi (New Jersey Institute of Technology) |
| 240 | A Multimodal AI Acceleration with Dynamic Pruning and Run-time Configuration | Hyunwoo Oh, Hanning Chen, Sanggeon Yun, Yang Ni (University of California, Irvine); Behnam Khaleghi (Qualcomm); Fei Wen (Samsung); Mohsen Imani (University of California, Irvine) |
| 245 | Performance Modeling and Comparisons of an FPGA-based Direct Simulation Monte Carlo Solver | Saleen Bhattarai, Edwin Peters (The University of New South Wales Canberra); Sean O’Byrne (The Australian National University); David Petty (The University of New South Wales Canberra) |
| 258 | SNIC-DSM: SmartNIC-based Distributed Shared Memory | Hemanth Ramesh, Naarayanan Rao VSathish, Edson Horta (Virginia Tech); Antonio Barbalace (The University of Edinburgh); Binoy Ravindran (Virginia Tech) |
| 261 | Multi-FPGA Synchronization and Data Communication for Quantum Control and Measurement | Yilun Xu, Abhi Rajagopala, Neelay Fruitwala, Gang Huang (Lawrence Berkeley National Laboratory) |
| 295 | iSEW: in-Sensor Embedded Watermarking for Secure Imaging | Sepehr Tabrizchi (University of Illinois Chicago); Shaahin Angizi (New Jersey Institute of Technology); Arman Roohi (University of Illinois Chicago) |