Abstract:<\/strong><\/p>\n\n\n\nDecades ago computers were pets. They sat on our desktops, had names and we cared for them as individuals. More recently, in addition to pets, computers have become cattle. They are out in the field, are identified by numbers, and if one dies it is replaced without associated mourning. The same transition is happening to hardware accelerators, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), which can now be considered cattle in cloud computers. A new model for cloud computing is disaggregation, which allows users to flexibly acquire and allocate the computing resources they need. The serverless programming model provides an abstraction for decomposing applications to map onto disaggregated hardware. Such disaggregated hardware is frequently connected directly to the network without the need or delay associated with host intervention. <\/p>\n\n\n\n
In this talk, I will focus on network-attached FPGAs available in the Open Cloud Testbed (OCT) https:\/\/octestbed.org\/. I will discuss the hardware model and programming paradigm of accelerators as cattle and applications that benefit from hardware directly to the network. I will also discuss security issues that arise from this model. Network-connected hardware can serve both as an attacker and as a defender from security breaches. FPGAs usually do not run an operating system, so there are no checks on the data sent out on the network. Thus, they can easily launch attacks such as Denial of Service (DoS) by flooding the network with packets. These FPGAs can also monitor traffic on the network directly, and identify such attacks. Nowadays, FPGAs are both pets and cattle, as well as having the potential to be either the attacker or the defender in disaggregated cloud computing. Whatever the question, FPGAs are the answer.<\/p>\n\n\n\n
Bio:<\/strong><\/p>\n\n\n\nMiriam Leeser<\/strong> has been designing with FPGAs since they first emerged as pets. She is a Professor of Computer Engineering at Northeastern University and head of the Reconfigurable Computing Laboratory. She has conducted research in floating point implementations, unsupervised learning, medical imaging, and privacy preserving data processing. Throughout her career, she has been funded by both government agencies and companies, including AMD, DARPA, NSF, Google, and MathWorks. She is the recipient of a Fulbright Scholar Award and a Charter Member of the IEEE Computer Society Distinguished Contributor Recognition Program. Her current research focus is on FPGAs for wireless communications as well as FPGAs in the data center.<\/p>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
Keynote I: Can Deep Learning Broaden the Participation of FPGA Designs? Jason Cong UCLA Computer Science Department Director, Center for Domain-Specific Computing (CDSC) https:\/\/vast.cs.ucla.edu\/people\/faculty\/jason-cong Abstract: Given that there are at least 30X more software designers than hardware designers based on the data from US Bureau of Labor Statistics, it is important to get many more … <\/p>\n
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