Monday – May 6<\/strong><\/h2>\n\n\n\n

\u2605<\/mark> indicates best paper candidate<\/em><\/p>\n\nDataset Available \nDataset Reviewed \nDataset Reproducible \n\n\n\n

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8:00 am – 8:45 am<\/td>	Registration Open and Coffee\/Tea (Breakfast on your own)<\/td><\/tr>
8:45 am – 9:00 am<\/td>	Opening<\/span><\/strong><\/td><\/tr>
9:00 am – 10:00 am<\/td>	Keynote: Can Deep Learning Broaden the Participation of FPGA Designs?<\/strong><\/mark><\/a> <\/strong><\/mark>Speaker: Jason Cong, UCLA <\/mark><\/td><\/tr>
10:00 am – 10:45 am<\/td>	Poster Session A<\/mark><\/strong><\/a> and Coffee\/Tea Break<\/td><\/tr>
10:45 am – 12:15 pm<\/td>	Session 1 – Applications<\/mark><\/strong> Chair: Peipei Zhou (University of Pittsburgh)<\/td><\/tr>
<\/td>	Bandwidth Efficient Homomorphic Encrypted Discrete Fourier Transform Acceleration on FPGA <\/strong> Zhihan Xu, Yang Yang (University of Southern California); Rajgopal Kannan (DEVCOM Army Research Lab); Viktor K. Prasanna (University of Southern California)<\/td><\/tr>
<\/td>	High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs<\/strong> Mohamed W Hassan, Hatem Ltaief, Suhaib A Fahmy (KAUST)<\/td><\/tr>
<\/td>	PCQ: Parallel Compact Quantum Circuit Simulation<\/strong> (short paper) \u2605<\/mark> Shuang Liang, Yuncheng Lu, Ce Guo, Wayne Luk, Paul H J Kelly (Imperial College London)<\/td><\/tr>
<\/td>	DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP<\/strong> (journal track)<\/strong> Tamimi, Sajjad (Technical University of Darmstadt – Embedded Systems and Applications Group); Bernhardt, Arthur (Reutlingen University – Data Management Lab); Stock, Florian (Technical University of Darmstadt – Embedded Systems and Applications Group); Petrov, Ilia (Reutlingen University – Data Management Lab); Koch, Andreas (Technische Universit\u00e4t Darmstadt – Embedded Systems and Applications Group)<\/td><\/tr>
<\/td>	PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA (journal track, no presentation)<\/strong> Sun, Mingqian (Southeast University – School of Cyber Science and Engineering) Xie, Guangwei (Fudan University – School of Computer Science); Zhang, Fan (National Digital Switching System Engineering and Technological Research Center); Guo, Wei (National Digital Switching System Engineering and Technological Research Center); Fan, Xitian (Shanghai Hongzhen Information Technology Co.,Ltd); Li, Tianyang (National Digital Switching System Engineering and Technological Research Center); Chen, Li (National Digital Switching System Engineering and Technological Research Center); Du, Jiayu (Purple Mountain Laboratories)<\/td><\/tr>
12:15 pm – 1:30 pm<\/td>	Lunch<\/td><\/tr>
1:30 pm – 2:45 pm <\/td>	Session 2 – Arithmetic<\/mark><\/strong> Chair: Mark Shand (Waymo)<\/td><\/tr>
<\/td>	HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory<\/strong> Abdul Rehman Tareen, Marius Meyer, Christian Plessl, Tobias Kenter (Paderborn University)<\/td><\/tr>
<\/td>	Efficient 8-bit Matrix Multiplication on Intel Agilex-5 FPGAs \u2605<\/mark> <\/strong>Sergey Gribok, Bogdan Pasca (Intel)<\/td><\/tr>
<\/td>	Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs <\/strong>Endri Taka, Dimitrios Gourounas, Andreas Gerstlauer, Diana Marculescu (The University of Texas at Austin); Aman Arora (Arizona State University)<\/td><\/tr>
<\/td>	DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration (journal track) <\/strong>Vakili, Shervin (Institut national de la recherche scientifique); Vaziri, Mobin (Polytechnique Montr\u00e9al); Zarei, Amirhossein (Institut national de la recherche scientifique); Langlois, Pierre (Ecole Polytechnique de Montreal)<\/td><\/tr>
2:45 pm – 3:00 pm <\/td>	Break<\/td><\/tr>
3:00 pm – 4:20 pm<\/td>	Session 3 – Machine Learning I<\/mark><\/strong> Chair: Cong “Callie” Hao (Georgia Institute of Technology)<\/td><\/tr>
<\/td>	GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA <\/strong>Bingyi Zhang (University of Southern California); Rajgopal Kannan, Carl Busart (DEVCOM Army Research Lab); Viktor K. Prasanna (University of Southern California)<\/td><\/tr>
<\/td>	PQA: Exploring the Potential of Product Quantization in DNN Hardware Acceleration<\/strong> (journal track)<\/strong> AbouElhamayed, Ahmed F. (Cornell University – Electrical and Computer Engineering); Cui, Angela (Cornell University); Fernandez-Marques, Javier (Flower Labs); Lane, Nicholas D. (University of Cambridge – Department of Computer Science and Technology); Abdelfattah, Mohamed S. (Cornell University – ECE)<\/td><\/tr>
<\/td>	Accelerating ViT Inference on FPGA through Static and Dynamic Pruning<\/strong> Dhruv Parikh, Shouyi Li, Bingyi Zhang (University of Southern California); Rajgopal Kannan, Carl Busart (DEVCOM Army Research Lab); Viktor K Prasanna (University of Southern California)<\/td><\/tr>
<\/td>	LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA<\/strong> (short paper) Shuxin Yang, Chenchen Ding (Southern University of Science and Technology, China); Mingqiang Huang (Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences); Kai Li, Zikun Wei, Hantao Huang, Hao Yu (Southern University of Science and Technology, China)<\/td><\/tr>
<\/td>	LGBM2VHDL: Mapping of LightGBM Models to FPGA<\/strong> (short paper) Tom\u00e1\u0161 Mart\u00ednek (Brno University of Technology); Jan Ko\u0159enek, Tom\u00e1\u0161 \u010cejka (CESNET, z. s. p. o.)<\/td><\/tr>
4:20 pm – 6:00 pm<\/td>	Break<\/td><\/tr>
6:00 pm – 8:00 pm<\/td>	Banquet<\/mark><\/strong>, Demo Night, and Ph.D. Forum<\/mark><\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n Tuesday – May 7 <\/strong><\/h2>\n\n\n\n 8:00 am – 9:00 am<\/td> Registration Open and Coffee\/Tea (Breakfast on your own)<\/td><\/tr> 9:00 am – 10:00 am<\/td> Keynote: Pets vs Cattle:  Heterogeneous Systems in the 21st Century.<\/mark><\/strong><\/a> <\/strong><\/mark>Miriam Leeser (Northeastern University)<\/td><\/tr> 10:00 am – 10:45 am<\/td> Poster Session B<\/mark><\/a><\/strong> and Coffee\/Tea Break<\/td><\/tr> 10:45 am – 12:15 pm<\/td> Session 4 – Compilation & CAD Tool<\/mark><\/strong><\/span><\/strong> Chair: Jason Anderson (University of Toronto) <\/span><\/strong><\/td><\/tr> <\/td> Toward FPGA Intellectual Property (IP) Encryption from Netlist to Bitstream (journal track) <\/strong>Hutchings, Daniel; Taylor, Adam; Goeders, Jeff (Brigham Young University)<\/td><\/tr> <\/td> LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization<\/strong> Rishov Sarkar, Rachel Paul, Cong (Callie) Hao (Georgia Institute of Technology)<\/td><\/tr> <\/td> A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs<\/strong> \u2605<\/mark> Zhili Xiong, Rachel Selina Rajarathnam, David Z. Pan (The University of Texas at Austin)<\/td><\/tr> <\/td> Synthesis of LUT Networks for Random-Looking Dense Functions with Don’t Cares – Towards Efficient FPGA Implementation of DNN<\/strong> (short paper) \u2605<\/mark> Yukio Miyasaka, Alan Mishchenko (UC Berkeley); Nicholas Fraser (AMD); John Wawrzynek (UC Berkeley)<\/td><\/tr> <\/td> A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints<\/strong> (short paper) Qin Luo, Xinshi Zang, Qijing WANG (The Chinese University of Hong Kong); Fangzhou Wang (Cadence Design Systems); Evangeline F.Y. Young (The Chinese University of Hong Kong); Martin D.F. Wong (Hong Kong Captist University)<\/td><\/tr> 11:35 pm – 12:15 pm<\/td> <\/td><\/tr> 12:15 pm – 1:30 pm<\/td> Lunch<\/td><\/tr> 1:30 pm – 2:50 pm<\/td> Session 5 – Architecture and CGRA<\/mark><\/strong> Chair: Suhaib Fahmy (King Abdullah University of Science and Technology)<\/td><\/tr> <\/td> HardCilk: Cilk-like Task Parallelism for FPGAs<\/strong> \u2605<\/mark> Mohamed Mahfouz Shahawy, Canberk S\u00f6nmez, Cemalettin Cem Belentepe, Paolo Ienne (EPFL)<\/td><\/tr> <\/td> Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams <\/strong>Rami Beidas, Jason H. Anderson (University of Toronto)<\/td><\/tr> <\/td> MPC-Wrapper: Fully Harnessing the Potential of Samsung Aquabolt-XL HBM2-PIM on FPGAs <\/strong>Jinwoo Choi, Yeonan Ha, Hanna Cha, Seil Lee, Sungchul Lee (Yonsei University); Jounghoo Lee (Yonsei University \/ MangoBoost); Shin-haeng Kang (Samsung Electronics); Bongjun Kim, Hanwoong Jung (Samsung Advanced Institute of Technology); Hanjun Kim, Youngsok Kim (Yonsei University)<\/td><\/tr> <\/td> FINESSD: Near-Storage Feature Selection with Mutual Information for Resource-Limited FPGAs<\/strong> Nikolaos Kyparissas, Gavin Brown, Mikel Lujan (The University of Manchester)<\/td><\/tr> 2:50 pm – 3:00 pm <\/td> Coffee Break<\/span><\/td><\/tr> 3:00 pm – 4:20 pm<\/td> Session 6 – Machine Learning 2<\/mark><\/strong> Chair: Mohamed Abdelfattah (Cornell University) <\/td><\/tr> <\/td> Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference (journal track)<\/strong> Chen, Hongzheng (Cornell University); Zhang, Jiahao (Tsinghua University); Du, Yixiao (Cornell University); Xiang, Shaojie (Cornell University); Yue, Zichao (Cornell University); Zhang, Niansong (Cornell University); Cai, Yaohui (Cornell University); Zhang, Zhiru (Cornell University)<\/td><\/tr> <\/td> SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction <\/strong>Petros Toupas (Imperial College London, UK – Information Technologies Institute (ITI)\/CERTH, GR); Zhewen Yu, Christos-Savvas Bouganis (Imperial College London, UK); Dimitrios Tzovaras (Information Technologies Institute (ITI)\/CERTH, GR)<\/td><\/tr> <\/td> HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures (journal track)<\/strong> Zhao, Chenfeng (Washington University in St Louis, Computer Science & Engineering Department); Faber, Clayton J. (Washington University in St Louis – Computer Science & Engineering); Chamberlain, Roger D (Washington University – Computer Science and Engineering); Zhang, Xuan (Northeastern University)<\/td><\/tr> <\/td> MRH-GCN: A Novel and Efficient GCN Accelerator for Multi-Relation Heterogeneous Graph <\/strong>(short paper) Wenlu Peng, Jianjun Chen, Wenjin Huang (Sun Yat-sen University); Yihua Huang (Sun-Yat-sen University)<\/td><\/tr> <\/td> A Novel FPGA Accelerator of R(2+1) D<\/strong> (short paper) Dehao Xiang, Chenyang Li, Wenjin Huang (Sun Yat-sen University); Yihua Huang (Sun-Yat-Sen University)<\/td><\/tr> 4:20 pm – 5:00 pm<\/td> Closing and Award Ceremony <\/span><\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n <\/p>\n","protected":false},"excerpt":{"rendered":" FCCM 2024 Program *All times shown in the EST (UTC-5) *Breakfast is not provided. Sunday (May 5) and Wednesday (May 8): Workshops and Tutorials Sunday – May 5 12:00 pm – 5:00 pm Registration Open 12:30 pm \u2013 5:00 pm Tutorials and Workshops 6:00 pm – 9:00 pm Sunday’s Reception and PanelCHIPS ACT, AI, Quantum … <\/p>\n Continue reading “Technical Program 2024”<\/span><\/a><\/p>\n","protected":false},"author":581,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/pages\/3443"}],"collection":[{"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/users\/581"}],"replies":[{"embeddable":true,"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/comments?post=3443"}],"version-history":[{"count":10,"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/pages\/3443\/revisions"}],"predecessor-version":[{"id":3643,"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/pages\/3443\/revisions\/3643"}],"wp:attachment":[{"href":"https:\/\/www.wp.fccm.org\/wp-json\/wp\/v2\/media?parent=3443"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}