| Mehdi Moghaddamfar (SAP SE - TU Dresden), Christian Färber (Intel Corporation), Norman May (SAP SE), Wolfgang Lehner and Akash Kumar (TU Dresden) |
FPGA-Based Database Query Processing on Arbitrarily Wide Tables |
1 |
| Anqi Guo (Boston University), Tong Geng (Pacific Northwest National Laboratory), Yongan Zhang (Rice University), Pouya Haghi, Chunshu Wu (Boston University), Cheng Tan (Microsoft), Yingyan Lin (Rice University), Ang Li (Pacific Northwest National Laboratory) and Martin Herbordt (Boston University) |
FCsN: A FPGA-Centric SmartNIC Framework for Neural Networks |
1 |
| Gyeongcheol Shin and Joo-Young Kim (KAIST) |
OpenMDS: An Open-Source Shell Generation Framework for High Performance Accelerator Design on Multi-Die FPGAs |
1 |
| Ralf Kundel (Technical University of Darmstadt), Leonhard Nobach, Hans-Joerg Kolbe (Deutsche Telekom Technik GmbH), Tobias Meuser and Ralf Steinmetz (Technical University of Darmstadt) |
FPGA-assisted Massive Packet Queueing and Traffic Shaping at the Network Edge |
1 |
| Lewis McLaughlin, Louise Crockett and Robert Stewart (Universiity of Strathclyde) |
A New Design Workflow for PYNQ Supported Xilinx Platforms Utilising the Simulink Environment for Vivado IPI Abstraction |
1 |
| Rushi Patel, Pouya Haghi (Boston University), Shweta Jain, Andriy Kot, Venkata Krishnan (Intel Corporation), Mayank Varia and Martin Herbordt (Boston University) |
COPA Use Case: Distributed Secure Joint Computation |
1 |
| Weikang Qiao, Licheng Guo (UCLA), Zhenman Fang (Simon Fraser University), Mau-Chung Frank Chang and Jason Cong (UCLA) |
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs |
1 |
| Mengshu Sun (Northeastern University), Sheng Lin, Shan Liu, Songnan Li (Tencent Media Lab), Yanzhi Wang (Northeastern University), Wei Jiang and Wei Wang (Tencent Media Lab) |
Hardware-Friendly Acceleration for Deep Neural Networks with Micro-Structured Compression |
1 |
| Jihwan Cho, Dalta Imam Maulana and Wanyeong Jung (Korea Advanced Institute of Science and Technology) |
A Near-Memory Radix Sort Accelerator with Parallel 1-bit Sorter |
1 |
| Lina Sawalha, Tawfiq Abuaita, Martin Cowely, Sergei Akhmatdinov and Adam Dubs (Western Michigan University) |
Accurate Performance and Power Prediction for FPGAs Using Machine Learning |
1 |
| Jennifer Smith, John Bailey and Benjamin Mazin |
Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA Design |
1 |
| Seyed Alireza Damghani and Kenneth B. Kent (University of New Brunswick) |
Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTR |
2 |
| Yuan Meng, Hongjiang Men and Viktor Prasanna (University of Southern California) |
Accelerating Deformable Convolution Networks |
2 |
| Hanning Chen and Mohsen Imani (University of California, Irvine) |
Density-Aware Parallel Hyperdimensional Genome Sequence Matching |
2 |
| Cornelia Wulf, Najdet Charaf and Diana Goehringer (Technische Universitaet Dresden) |
Scheduling of Hardware Tasks in Reconfigurable Mixed-Criticality Systems |
2 |
| Rushi Patel, Pouya Haghi (Boston University), Shweta Jain, Andriy Kot, Venkata Krishnan (Intel Corporation), Mayank Varia and Martin Herbordt (Boston University) |
COPA Use Case: Distributed Secure Joint Computation |
2 |
| Tomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa and Teruaki Ishizaki (Nippon Telegraph and Telephone Corporation) |
FPGA-based Accelerators System with Low Latency Autonomous DMA Engine |
3 |
| Najdet Charaf, Christoph Tietz and Diana Goehringer (Technische Universität Dresden) |
MaNaBIT: A Versatile Tool for Manipulating and Analyzing FPGA Bitstreams |
3 |
| Junning Fan and Oliver Diessel (UNSW) |
On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs |
3 |
| Yun Wang, Qiang Liu and Shun Yan (Tianjin University) |
DQI: A Dynamic Quantization Method for Efficient Deep Neural Network Inference Accelerators |
3 |
| Saeid Gorgin, Mohammad Hosein Gholamrezaei, Danial Javaheri and Jeong-A Lee (Chosun University) |
An Efficient FPGA Implementation of k-Nearest Neighbors (k-NN) via Online Arithmetic |
3 |
| Xu Shengjun, Huang Wenjin and Huang Yihua (Sun Yat-sen University) |
TFR-GCN: A GCN Accelerator with Tile-Fusing Strategy |
3 |
| Peng Xue (Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences), Lunshuai Pan, Litao Sun (School of Electronic Science and Engineering, Southeast University) and Mingqiang Huang (Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences) |
Dual-Line-Systolic Array for High Performance CNN Accelerator |
3 |
| Shaodong Zheng (Fuzhou University), Ruiqi Chen (Nanjing Qujike Info-tech Co., Ltd.), Yuhanxiao Ma (New York University), Zhengdong Kang (Fuzhou University), Chao Chen (Southeast University) and Shizhen Huang (Fuzhou University) |
Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators |
3 |
| Xingyue Qian, Jian Shi, Li Shi, Haoyang Zhang (Shanghai Jiao Tong University), Lijian Bian (Shanghai AnLogic Infotech Co., Ltd) and Weikang Qian (Shanghai Jiao Tong University) |
Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space Exploration |
3 |
| Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi (PETRA), Kenji Mizutani (NEC Corporation), Shigeru Nakamura, Tatsuya Usuki (PETRA) and Michihiro Koibuchi (National Institute of Informatics) |
A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks |
3 |
| Stewart Denholm and Wayne Luk (Imperial College) |
Mixed-Resource Compute Pools on FPGAs |
4 |
| Nicolai Fiege (University of Kassel), Patrick Sittel (Sartorius) and Peter Zipf (University of Kassel) |
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling |
4 |
| Emmmanuel Chailloux (Sorbonne University), Jocelyn Sérot (Blaise Pascal University) and Loïc Sylvestre (Sorbonne University) |
A Virtual Machine Approach for High-level FPGA Programming |
4 |
| Nick Brown (The University of Edinburgh) |
A programming model for developing Application Specific Dataflow Machines on FPGAs |
4 |
| Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang and Jason Cong (UCLA) |
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA |
4 |
| Jianyi Cheng, John Wickerson and George Constantinides (Imperial College London) |
Dynamic C-Slow Pipelining for HLS |
5 |
| Michalis Pardalos, Yann Herklotz and John Wickerson (Imperial College London) |
Resource Sharing for Verified High-Level Synthesis |
5 |
| Lana Josipovic (ETH Zurich); Axel Marmet, Andrea Guerrieri and Paolo Ienne (EPFL) |
Resource sharing in dataflow circuits |
5 |
| Tiancheng Xu, Scott Rixner and Alan Cox (Rice University) |
An FPGA Accelerator for Genome Variant Calling |
5 |
| Ecenur Ustun, Ismail San (Cornell University), Jiaqi Yin, Cunxi Yu (The University of Utah), and Zhiru Zhang (Cornell University) |
IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS |
5 |
| Xiang Li, Russell Tessier and Daniel Holcomb (University of Massachusetts Amherst) |
Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs |
5 |
