From RTL to Compute Acceleration using Vitis and Cloud Computing (Day 2)<\/strong><\/a><\/td>Parimal Patel (Xilinx)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\nIntel FPGA Cloud Services and Remote Learning<\/h1>\n\n\n\nDate: Sunday May 9<\/strong><\/p>\n\n\n\nOrganizer: Landis Lawrence (Intel)<\/strong><\/p>\n\n\n\nSpeaker<\/strong> Najmeh Nazari, Research Assistant, UC Davis School of Electrical and Computer Engineering<\/p>\n\n\n\nGain hands-on experience using Intel\u00ae FPGA development tools and kits\/accelerator cards in a remote environment. The first half of the course will focus on how to teach undergraduate level courses using Verilog\/Schematics\/Prebuilt IP and accessing Terasic\u2019s DE10-Lite kit in a remote environment. Topics covered are network setup, installation, compilation and download. The second half of the course will focus on graduate level heterogeneous computing teaching and research on the Intel\u00ae FPGA Devcloud and Hardware Accelerator Research Program clouds . These Intel cloud services have the latest configurations of Quartus (RTL), OpenCL, OneAPI and Openvino workload compilation in a XEON+ Arria 10\/Stratix 10 FPGA development environment available free to the academic community. Labs include using the Intel FPGA Devcloud for dpc++ workload compilations and performance analysis.<\/p>\n\n\n\n FPGA High-Level Synthesis: Good Practices for Quality and Productivity<\/h1>\n\n\n\nDate: Sunday May 9<\/strong><\/p>\n\n\n\nOrganizer: Vanderlei Bonato (USP, Brazil)<\/strong><\/p>\n\n\n\nSpeakers<\/strong><\/p>\n\n\n\n- BSc. Andre B. Perina (Institute of Mathematics and Computer Sciences – University of S\u00e3o Paulo – Brazil)<\/li>
- Dr. Leandro S. Rosa (Event-Driven Perception – Istituto Italiano di Tecnologia \u2013 Italia)<\/li>
- Dr. Vanderlei Bonato (Institute of Mathematics and Computer Sciences – University of S\u00e3o Paulo – Brazil)<\/li><\/ul>\n\n\n\n
This tutorial is orientated to starters in the HLS world. It brings a broad view about HLS, connecting the software-like input to functional and temporal simulations, and the final hardware design. The goal is to understand the effects of data type, arithmetic, loops, interfaces and memory organisation inferred from software, providing to the designers a set of good practices to improve the final hardware quality while minimising the implementation efforts. Practical experiments will be conducted in Vivado and Vitis HLS and the participants are motivated to replicate the experiments remotely and to share their experiences. For the tutorial, participants are encouraged to install in advance the Vitis Core Development Kit – 2020.2 (select Vitis on the Xilinx Unified Installer to enable Vivado Design Suite to be installed together).<\/p>\n\n\n\n
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