List of Accepted Posters

A General Video Processing Framework on Edge Computing FPGAs
Feng Yu (Southeast University, China), He Li (University of Cambridge, UK), Rongshi Dai (Southeast University, China), Yongming Tang (Southeast University, China)

A Tunable Dual-Edge Time-to-Digital Converter
Colin Drewes (University of California, San Diego), Steven Harris (University of California, San Diego), Winnie Wang (University of California, San Diego), Richard Appen (University of California, San Diego), Olivia Weng (University of California, San Diego), Ryan Kastner (University of California, San Diego), William Hunter (Georgia Tech Research Institute), Christopher McCarty (Georgia Tech Research Institute), Dustin Richmond (University of Washington)

Accelerating Large-Scale Nearest Neighbor Search with Computational Storage Device
Ji-Hoon Kim (School of Electrical Engineering, KAIST, Republic of Korea), Yeo-Reum Park (School of Electrical Engineering, KAIST, Republic of Korea), Jaeyoung Do (Microsoft Research, USA), Soo-Young Ji (Memory Business, Samsung Electronics, Republic of Korea), Joo-Young Kim (School of Electrical Engineering, KAIST, Republic of Korea)

ARC: Reconfigurable Cache Security Assurance with Application-Specific Randomized Mapping in FPGA-Based Heterogeneous Computing
Sanjay Gandham (University of Central Florida, USA), Rakin Muhammad Shadab (University of Central Florida, USA), Mingjie Lin (University of Central Florida, USA)

AutoTEA: Automated Transistor-Level Efficient and Accurate Optimization for GRM FPGA Design
Yanze Li (State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China), Yufan Zhang (State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China), Jiafeng Liu (State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China), Jian Wang (State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China), Jinmei Lai (State Key Lab of ASIC & System, School of Microelectronics, Fudan University, China), Gang Qu (University of Maryland, College Park, United States)

Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography
Daniele Passaretti (Otto von Guericke University Magdeburg; Research Campus STIMULATE, Germany), Thilo Pionteck (Otto von Guericke University Magdeburg, Germany)

DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers
Jan Kubálek (CESNET a.l.e., Czech Republic), Jakub Cabal (CESNET a.l.e., Czech Republic), Martin Špinler (CESNET a.l.e., Czech Republic), Radek Iša (CESNET a.l.e., Czech Republic)

Edge Accelerator for Lifelong Deep Learning using Streaming Linear Discriminant Analysis
Duvindu Piyasena (Nanyang Technological University, Singapore), Siew-Kei Lam (Nanyang Technological University, Singapore), Meiqing Wu (Nanyang Technological University, Singapore)

Enabling OpenMP Task Parallelism on Multi-FPGAs
Ramon Nepomuceno (University of Campinas, Brazil), Renan Sterle (University of Campinas, Brazil), Guilherme Valarini (University of Campinas, Brazil), Marcio Pereira (University of Campinas, Brazil), Hervé Yviquel (University of Campinas, Brazil), Guido Araujo (University of Campinas, Brazil)

Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design
Chengyue Wang (Zhejiang University, China), Sitao Huang (University of Illinois, USA), Wen-Mei Hwu (University of Illinois, USA), Deming Chen (University of Illinois, USA)

FERMAT: FPGA-Accelerated Heterogeneous Computing Platform Near NVMe Storage
Yu Zou (University of Central Florida), Mingjie Lin (University of Central Florida)

FFIVE: An FPGA Framework for Interactive VNF Environments
Juan Camilo Vega (University of Toronto, Canada), Mohammad Ewais (University of Toronto, Canada), Alberto Leon Garcia (University of Toronto, Canada), Paul Chow (University of Toronto, Canada)

Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs
Tiandong Zhao (University of California, Los Angeles), Yunxuan Yu (University of California, Los Angeles), Kun Wang (University of California, Los Angeles), Lei He (University of California, Los Angeles)

Near-Storage Acceleration of Database Query Processing with SmartSSDs
Mohammadreza Soltaniyeh (Rutgers University), Veronica Lagrange Moutinho Dos Reis (Samsung Semiconductor, Inc), Matthew Bryson (Samsung Semiconductor, Inc), Richard Martin (Rutgers University), Santosh Nagarakatte (Rutgers University)

NullaNet Tiny: Ultra-low-Latency DNN Inference Through Fixed-Function Combinational Logic
Mahdi Nazemi (University of Southern California, USA), Arash Fayyazi (University of Southern California, USA), Amirhossein Esmaili (University of Southern California, USA), Atharva Khare (University of Southern California, USA), Soheil Nazar Shahsavani (University of Southern California, USA), Massoud Pedram (University of Southern California, USA)

ONT-X: An FPGA Approach to Real-Time Portable Genomic Analysis
Ramachandra Chakenalli Nanjegowda (University of Utah), Gurpreet Kalsi (Intel Labs), Anirban Nag (University of Utah), Kamlesh Pillai (Intel Labs), Sreenivas Subramoney (Intel Labs), Rajeev Balasubramonian (University of Utah)

Particle Mesh Ewald for Molecular Dynamics in OpenCL on an FPGA Cluster
Lawrence C. Stewart (Silicon Therapeutics, USA), Carlo Pascoe (Silicon Therapeutics, USA), Emery Davis (Silicon Therapeutics, USA), Brian W. Sherman (Silicon Therapeutics, USA), Martin Herbordt (Boston University, USA), Vipin Sachdeva (Silicon Therapeutics, USA)

Pharos: a Performance Monitor for Multi-FPGA Systems
Arzhang Rafii (University of Toronto, Canada), Paul Chow (University of Toronto, Canada), Welson Sun (Alibaba Group, Canada)

Reconfigurable Synthesizable Synchronization FIFOs
Ameer M. S. Abdelhadi (University of Toronto), He Li (University of Cambridge)

Scalable FPGA Median Filtering via a Directional Median Cascade
Oscar Rahnama (University of Oxford, UK), Stuart Golodetz (University of Oxford, UK), Tommaso Cavallari (University of Oxford, UK), Philip Torr (University of Oxford, UK)

Scheduling Persistent and Fully Cooperative Instructions
Yu Yang (School of EECS, KTH Royal Institute of Technology, Sweden), Ahmed Hemani (School of EECS, KTH Royal Institute of Technology, Sweden), Kolin Paul (Indian Institute of Technology Delhi, India)

TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths
Zhengzheng Ma (Peking University), Guojie Luo (Peking University)

TwinDNN: A Tale of Two Deep Neural Networks
Hyunmin Jeong (University of Illinois, Urbana-Champaign), Deming Chen (University of Illinois, Urbana-Champaign)

Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices
Evangelos Mageiropoulos (Foundation for Research and Technology Hellas (FORTH), Greece), Nikolaos Chrysos (Foundation for Research and Technology Hellas (FORTH), Greece), Nikolaos Dimou (Foundation for Research and Technology Hellas (FORTH), Greece), Manolis Katevenis (Foundation for Research and Technology Hellas (FORTH), Greece)

An FPGA Based Hardware Accelerated Framework for Solar Spectra Matching with Parameterized Matched Filter IP Core
Verjina Torosian Khouygani (California State University, Northridge, USA), Shahnam Mirzaei (California State University, Northridge, USA), Christian Beck (National Science Observatory, USA), Debi Prasad Choudhary (California State University, Northridge, USA)

Time-Domain FPGA Power Delivery Network Characterization Methodology
Yanran P. Chen (Xilinx, Inc., USA), Martin L. Voogel (Xilinx, Inc., USA), Ed Priest (Xilinx, Inc., USA), Qian Wang (Xilinx, Inc., USA), Ranjeeth Doppalapudi (Xilinx, Inc., USA), Praful Jain (Xilinx, Inc., USA)