Rajesh Kedia

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May 21, 2020 at 3:44 am in reply to: Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC #1715

Rajesh Kedia
Participant

It is clear. Thanks.

May 20, 2020 at 2:09 am in reply to: Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC #1711

Rajesh Kedia
Participant

Very nice and comprehensive work. The presentation was very clear and well explained.

I have one question: You mentioned that the AXI transactions reach the memory controller but are not processed as the bus is stalled by a misbehaving IP. I was just wondering if there is an alternative option of tuning the memory controller to address such stalls?

May 12, 2020 at 3:28 am in reply to: Comments Please! #1695

Rajesh Kedia
Participant

I am attending FCCM for the first time (have attended other conferences though) and I liked the virtual format a lot. I guess, this is a new futuristic direction for the conferences. The hybrid option would also be nice to explore, once situation becomes normal.
Thanks a lot.

May 12, 2020 at 3:11 am in reply to: Best Paper Award Winner: Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on #1694

Rajesh Kedia
Participant

Nice work and nice presentation. Congratulations to the authors for winning the best paper award.

I have one simple clarification – the DSPs are not used for adders in CFP and Posit. Any specific reason?
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