[francesco.restuccia]

Hello Rajesh, thank you for the feedback!
To answer your question, this would be possible in case a memory transaction would involve just the misbehaving hardware accelerator and the memory controller. However, in modern SoC, requests for transactions and data are routed into a way more complicated network made of multiple AXI interconnects, buffers, etc. Each of them expects that each request for transaction is completed according to the AXI standard to route correctly the data into the network. This means that when a misbehavior happens, all the components of the network can fall in a compromised state.

In other words, solving the problem at the memory controller (maybe aborting the misbehaving transaction(s)?) would not bring back to a safe state the rest of the network, which may be still in an inconsistent state (hence not able to route (serve) further requests/data). Another level of complexity is that this depends on the actual implementation of the network and, in general, the documentation of the modern SoCs do not disclose this kind of details (unfortunately).
Concluding, I don’t see a way to solve this problem at the memory controller in a safe way.
I hope my explanation is clear. Let me know if I answer your question or you need a further explanation!

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