Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs FCCM Main Page › Forums › Poster Session 5 – Machine Learning 1 › Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs This topic has 0 replies, 1 voice, and was last updated 1 month, 3 weeks ago by Ken Eguro. Log In Register Lost Password Viewing 0 reply threads Author Posts April 8, 2020 at 6:28 am #1201 Ken EguroKeymaster Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs – Link for PDF Akira Jinguji (Tokyo Institute of Technology), Shimpei Sato (Tokyo Institute of Technology), and Hiroki Nakahara (Tokyo Institute of Technology) /proceedings/2020/Presentations/PosterSession5/1.mp4 Author Posts Log In Register Lost Password Viewing 0 reply threads You must be logged in to reply to this topic. Log In Username: Password: Keep me signed in Log In