High Density 8-bit Multiplier Systolic Arrays for FPGA FCCM Main Page › Forums › Paper Session 3 – Arithmetic › High Density 8-bit Multiplier Systolic Arrays for FPGA This topic has 0 replies, 1 voice, and was last updated 1 month, 3 weeks ago by Ken Eguro. Log In Register Lost Password Viewing 0 reply threads Author Posts April 8, 2020 at 5:55 am #1160 Ken EguroKeymaster High Density 8-bit Multiplier Systolic Arrays for FPGA – Link for PDF Martin Langhammer (Intel Corporation), Sergey Gribok (Intel Corporation), and Gregg Baeckler (Intel Corporation) Link to presentation Author Posts Log In Register Lost Password Viewing 0 reply threads You must be logged in to reply to this topic. Log In Username: Password: Keep me signed in Log In