Best Paper Award Winner: Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on

[Ken Eguro]

Best Paper Award Winner: Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs – Link for PDF
Lukas Sommer (TU Darmstadt), Lukas Weber (TU Darmstadt), Martin Kumm (Fulda University of Applied Sciences), and Andreas Koch (TU Darmstadt)

[Steve_Casselman]

In machine learning you have quality of results. For example in classification, did the circuit correctly classify all input data. Was there any difference in QoR in using the different arithimatic formats?

[Rajesh Kedia]

Nice work and nice presentation. Congratulations to the authors for winning the best paper award.

I have one simple clarification – the DSPs are not used for adders in CFP and Posit. Any specific reason?

[Lukas Weber]

Frist of all, thanks for your Questions.

@Steve Casselman: In our paper, we basically try to normalize for quality of results. Instead of using a certain data-format and evaluating how good the QoR is, we instead used the flexibility of the corresponding operators to fine-tune them to a certain QoR-expectancy. In our case this was a maximum error of 10^-6 for the resulting log-likelihoods. Thus, the QoR of all three formats is as close as possible to this margin, and from there, we evaluated the resource/energy-requirements and performance. The result was basically: When normalized for a given QoR, LNS shines in multiplication-heavy SPNs, while CFP shines in addition-heavy SPNs.

@Rajesh Kedia: Thanks for the congratulations, much appreciated :). Considering the DSPs, we had no specific evaluation for whether or not to use DSPs for adders in this paper. In our experience and previous work, we have made the following observations, though:
1) Using DSPs too heavily on the VC709 has a very big impact on clock frequency, probably due to contention of the corresponding routing resources. This was especially visible in our prior work using FloPoCo 64bit operators.
2) In this work, the bitwidths of all operators are relatively small (Mantissa of CFP never exceeds 28 bits). Using a DSP (supporting 48 bit addition) is relatively “inefficient” use of the DSP.
These two observations are the main reasons behind this design choice.

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