Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms

[Ken Eguro]

Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms – Link for PDF
Yuan Meng (University of Southern California), Sanmukh Kuppannagari (University of Southern California), and Viktor Prasanna (University of Southern California)

[syed]

Hi! Great paper! The results are impressive and I liked the comparison between Xeon, Titan and U200. I was wondering how was your experience working with U200? Did you like the tool support from Xilinx? You mentioned you used TensorFlow – is the integration with the Xilinx tools mature enough for research work like this or did you have to write your own glue code to get things done between TensorFlow and U200 tooling?

Thank you!

[Yuan Meng]

Hi,
Thanks for your interest in our work.

In our case, we developed the accelerator in RTL coding, and the drivers porting the communication (through PCIe) between TensorFlow program on host CPU and FPGA accelerator had to be manually developed, and wrapped in Cython to be called from the python(TF) program. On Xilinx U200 side I used PCIe integrated IP block in Vivado.
However, I am aware that Xilinx Vitis or Pynq platform provides some high-level support to automate this process, it would definitely be interesting to try those out.

[Dustin Richmond]

Thank you for posting your question!

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