All times shown in PDT (UTC-7)
Sunday, April 28
All Sunday events are at the Sanford Consortium for Regenerative Medicine in the Roth Auditorium and the Bella Vista Caffe Terrace
RISC-V in Custom Computing Machines
3:30 – 5:00 PM PDT
Roth Auditorium
Presenters:
- David Donofrio, Lawrence Berkeley National Laboratory
- Farzad Fatollahi-Fard, Lawrence Berkeley National Laboratory
- John Leidel, Tactical Computing Labs
David, Farzad and John, leading researchers in RISC-V architecture, will present an overview of the processor from the FCCM perspective. The RISC-V community continues to grow and the widespread adoption of RISC-V based cores has led to well supported hardware implementations combined with feature-complete software toolchains. These open source designs rival, and are often superior to, commercial soft core offerings. Topics to be discussed include:
- Advantages/disadvantages compared to vendor provided soft processors
- The various RISC-V flavors and configuration options
- How to extend the instruction set to create custom instructions in the FPGA fabric
- Compiler tool chain and how to splice or download RISC-V programs onto the FPGA
- How to run standalone programs
- Examples or applications of RISC-V use in FPGA designs
Soft Processor Panel
5:30 – 7:00 PM PDT
Roth Auditorium
The panelists will offer their viewpoints on the roles and management of soft processor cores in custom computing machines. Topics include core microarchitectures, configurability and options, cache and memory hierarchy, interaction of soft and hard processors, interfaces to hard and soft IP blocks, compiler and debug tools, software stack and run time.
Panelists:
- Rob Aitken, ARM
- Mike Butts, Compute Forest
- Jan Gray, Gray Research
- Guy Lemieux, University of British Columbia and Founder, CEO of VectorBlox
- Ron Minnich, Google
- Lesley Shannon, Simon Fraser University
- Ted Speers, Microsemi
- Stephen Neuendorffer, Xilinx
Sunset Reception
7:00 – 8:30 PM PDT
Bella Vista Caffe Terrace
Monday, April 29
Technical Program
Qualcomm Institute Auditorium
(Bold Titles indicate best paper candidates)
| Time | Session Title (Chair) | Presentation Title | Authors |
|---|---|---|---|
| 8:00 | Breakfast | ||
| 8:30 | Opening | Opening Session | Ryan Kastner, André DeHon |
| 8:45 | Keynote (Jason Cong) | HoF induction, Keynote | Rahul Razdan Video Slides |
| 9:45 | Open Source Tools (Lesley Shannon) | Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs (short) | David Shah, Eddie Hung, Clifford Wolf, Miodrag Milanovic, Serge Bazanski and Dan Gisselquist |
| EFCAD – an Embedded FPGA CAD Tool Flow for Enabling On-Chip Self-Compilation (short) | Khoa Pham, Malte Vesper, Dirk Koch and Eddie Hung | ||
| Maverick: A Stand-alone CAD Flow for Partially Reconfigurable FPGA Modules | Dallon Glick, Jesse Grigg, Brent Nelson and Michael Wirthlin | ||
| 10:15 | Morning Break and Poster Session 1: Tools | Details | |
| 11:00 | Machine Learning 1 (Ro Cammarota) | An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs | Liqiang Lu, Jiaming Xie, Ruirui Huang, Xiaoyuan Cui, Jiansong Zhang, Wei Lin and Yun Liang |
| LUTNet: Rethinking Inference in FPGA Soft Logic | Erwei Wang, James Davis, Peter Cheung and George Constantinides | ||
| PIR-DSP: An FPGA DSP-block Architecture for Multi-Precision Deep Neural Networks | Seyedramin Rasoulinezhad, Hao Zhou, Ling Li Wang and Philip H.W. Leong | ||
| Towards Efficient Deep Neural Network Training by FPGA-based Batch-level Parallelism | Cheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk and Ce Guo | ||
| 12:20 | Lunch | Lunch | |
| 1:35 | Tools (Eli Bozorgzadeh) | CRoute: A Fast High-Quality Timing-driven Connection-based FPGA Router | Dries Vercruyce, Elias Vansteenkiste and Dirk Stroobandt |
| RapidRoute: Fast Assembly of Communication Structures on FPGAs (short) | Leo Liu, Jay Weng and Nachiket Kapre | ||
| Generic Connectivity-Based CGRA Mapping via Integer Linear Programming | Matthew J. P. Walker and Jason H. Anderson | ||
| LAMDA: Learning-Assisted Multi-Stage Autotuning for FPGA Design Closure (short) | Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu and Zhiru Zhang | ||
| Memory Mapping for Multi-Die FPGAs | Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk and Georgi Gaydadjiev | ||
| Impact of FPGA Architecture on Area and Performance of CGRA Overlays | Ian Taras and Jason Anderson | ||
| An FPGA-based BWT Accelerator for Bzip2 Data Compression (short) | Mau-Chung Frank Chang, Jason Cong, Zhenman Fang and Weikang Qiao | ||
| 3:10 | Afternoon Break and Poster Session 2: Neural Networks and Vision | Details | |
| 3:50 | Applications 1 (Christophe Bobda) | π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization | Shuzhen Qin, Qiang Liu, Bo Yu and Shaoshan Liu |
| Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata | Milan Ceska, Vojtěch Havlena, Lukas Holik, Jan Korenek, Ondrej Lengal, Denis Matousek, Jiří Matoušek, Jakub Semric and Tomas Vojnar | ||
| Active Stereo Vision with High Resolution on an FPGA | Marc Pfeifer, Philipp Scholl, Rainer Voigt and Bernd Becker | ||
| Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU | Licheng Guo, Ka Cheong Jason Lau, Zhenyuan Ruan, Peng Wei and Jason Cong | ||
| Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared Memory Platform | Yu Wang, James Hoe and Eriko Nurvitadhi | ||
| 5:30 | Break | ||
| 6:00 | Demo Night at Scripps Forum | Details | Grace Zgheib |
| 9:00 | End of Demo Night |
Poster Session 1: Tools
| Title | Authors |
|---|---|
| Automated Tool and Runtime Support for Fine-grain Reconfiguration in Highly Flexible Reconfigurable Systems | Rafael Zamacola, Alberto García Martínez, Javier Mora, Andrés Otero and Eduardo de La Torre |
| AutoPhase: Compiler Phase-Ordering for High-Level Synthesis with Deep Reinforcement Learning | Qijing Huang, Ameer Haj-Ali, William Moses, John Xiang, Ion Stoica, Krste Asanovic and John Wawrzynek |
| Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications | Norbert Deak, Octavian Creţ and Horia Hedeşiu |
| Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs | Michail Papadimitriou, Juan Fumero, Athanasios Stratikopoulos and Christos Kotselidis |
| Sonar: Writing Testbenches through Python | Varun Sharma, Naif Tarafdar and Paul Chow |
| Raparo: Resource-Level Angle-Based Parallel Routing for FPGAs | Minghua Shen and Nong Xiao |
| Automated acceleration of dataflow-oriented C applications on FPGA-based systems | Francesco Peverelli, Marco Rabozzi, Salvatore Cardamone, Emanuele Del Sozzo, Alex J. W. Thom, Marco Domenico Santambrogio and Lorenzo Di Tucci |
| Automated Design Space Exploration and Roofline Analysis for FPGA-based HLS Applications | Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Marco Domenico Santambrogio and Lorenzo Di Tucci |
| Formalizing loop-carried dependencies in Coq for high-level synthesis | Florian Faissole, George A. Constantinides and David Thomas |
Poster Session 2: Neural Networks and Vision
| Title | Authors |
|---|---|
| Exploring the Random Network of Hodgkin and Huxley Neurons with Exponential Synaptic Conductances on OpenCL FPGA Platform | Zheming Jin and Hal Finkel |
| A Scalable OpenCL-Based FPGA Accelerator For YOLOv2 | Ke Xu, Xiaoyun Wang and Dong Wang |
| Model-Extraction Attack against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis | Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki and Takeshi Fujino |
| SimBNN: A Similarity-Aware Binarized Neural Network Acceleration Framework | Cheng Fu, Shilin Zhu, Huili Chen, Farinaz Koushanfar, Hao Su and Jishen Zhao |
| KPynq: A Work-Efficient Triangle-Inequality based K-means on FPGA | Yuke Wang, Zhaorui Zeng, Boyuan Feng, Lei Deng and Yufei Ding |
| A High Throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor | Lili Liu, Xiaoqiang Xiang, Yuxiang Xie, Yongjie Li, Bo Yan and Jun Zhou |
| An OpenCL-based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform | Samah Rahamneh and Lina Sawalha |
Demo Night
6:00 – 8:30 PM PDT
Scripps Forum
Demo Night is an opportunity for people to show off their latest and greatest systems, tools, and technologies in a relaxed atmosphere. See the latest technology from industry, meet with the leading FCCM researchers, demonstrate the latest and greatest research, and receive early feedback on work in progress.
The list of Presenters and Demos is shown below
| Demo # | Authors | Title | Video Link (Optional) |
|---|---|---|---|
| 1 | Dan Pritsker and Colman Cheung | Monobit Wideband Receiver with Integrated Dithering in FPGA | |
| 2 | Martin Geier, Dominik Faller, Marian Brändle and Samarjit Chakraborty | Combined Energy and Latency Monitoring of a Zynq-based GigE Vision Acquisition/Processing Pipeline | Link |
| 3 | Michail Papadimitriou, Juan Fumero, Athanasios Stratikopoulos and Christos Kotselidis | Enabling Fast Prototyping and Acceleration of Java Programs onto Intel FPGAs with TornadoVM | |
| 4 | Georgi Gaydadjiev and Nils Voss | Performance Potability using MaxCompiler | |
| 5 | Jonathan Beaumont, Shane Fleming, Matthew Naylor, David Thomas, Andrew Brown, Andrey Mokhov and Simon Moore | POETS - Partial Ordered Event Triggered Systems | |
| 6 | Haggai Eran, Lior Zeno, Maroun Tork, Gabi Malka, Zsolt István and Mark Silberstein | A SmartNIC-based memcached Accelerator with NICA and ntl | |
| 7 | Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk and Steve Wilton | On-chip FPGA Debug Instrumentation for Machine Learning Applications | Link |
| 8 | Eddie Hung and David Shah | Yosys+nextpnr: Bet you can't say this tongue twister faster than I can bitstream | |
| 9 | Naif Tarafdar, Varun Sharma and Paul Chow | Telepathy: A Multi-FPGA, Multi-CPU Machine Learning Framework Deployed on a Hardware Stack | |
| 10 | Dallon Glick, Jesse Grigg, Brent Nelson and Michael Wirthlin | Maverick: A Stand-alone CAD Flow for Partially Reconfigurable FPGA Modules | |
| 11 | Richard Chamberlain and Marcus Weddle | FPGA Acceleration of Binary Weighted Neural Network Inference | Link |
| 12 | Dominique Meyer, Akhil Birlangi, Ryan Kastner and Falko Kuester | FPGA Accelerated Stereo Depth for Stereo-Panoramic Video and Scene Estimation | |
| 13 | Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel and Mircea Stan | Flexible, Highly-Parameterizable Encryption Modules in Chisel on RISC-V Cores | |
| 14 | Mineto Tsukada, Masaaki Kondo and Hiroki Matsutani | An FPGA-based On-device Sequential Learning Approach for Unsupervised Anomaly Detection | |
| 15 | Guy Lemieux | Running highly accelerated software on FPGA-based soft and hard processors | Link |
| 16 | Eugenio Culurciello, Sen Ma and Shanyuan Gao | Creating an AI-Generated Portrait via Style Transfer | |
| 17 | Alireza Khodamoradi, Ryan Kastner and Parimal Patel | Designing and Fast Prototyping with PYNQ and Vivado HLS | |
| 18 | John Lockwood | Real-time data in connected cities using Key Value Store in FPGA |
Tuesday, April 30
Technical Program
Qualcomm Institute Auditorium
(Bold Titles indicate best paper candidates)
| Time | Session Title (Chair) | Presentation Title | Authors |
|---|---|---|---|
| 8:00 | Breakfast | ||
| 8:30 | Simulation and Infrastructure (Wei Zhang) | MEG: A RISCV-based system simulation infrastructure for exploring memory optimization using FPGAs and Hybrid Memory Cube | Jialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha, Jonathan Ta and Jing Li |
| Enhancing Butterfly Fat Tree NoCs for FPGAs with lightweight flow control | Gurshaant Singh Malik and Nachiket Kapre | ||
| SimAcc: A Configurable Cycle-Accurate Simulator for customized accelerators on CPU-FPGAs SoCs | Konstantinos Iordanou, Oscar Palomar, John Mawer, Cosmin Gorgovan, Andy Nisbet and Mikel Lujan | ||
| 9:30 | Morning Break and Poster Session 3: Networking and Resource Sharing | Details | |
| 10:15 | Machine Learning 2 (John Lockwood) | Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA | Zhe Lin, Sharad Sinha and Wei Zhang |
| T2S-Tensor : Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations | Nitish Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher Hughes, Timothy Mattson, Pradeep Dubey | ||
| SparseHD: Algorithm-Hardware Co-Optimization for Efficient High-Dimensional Computing | Mohsen Imani, Sahand Salamat, Behnam Khaleghi, Mohammad Samragh, Farinaz Koushanfar and Tajana Rosing | ||
| Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs | Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory Chen, Phil Knag, Raghavan Kumar, Ram Krishnamurthy and Debbie Marr | ||
| 11:35 | Lunch | ||
| 12:50 | Programming (Ken Eguro) | Design Patterns for Code Reuse in HLS Packet Processing Pipelines | Haggai Eran, Lior Zeno, Zsolt István and Mark Silberstein |
| Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design | Jeferson Santiago da Silva, François-Raymond Boyer and J.M. Pierre Langlois | ||
| Templatised soft floating-point for High-Level Synthesis - Best Long Paper Award Winner! | David Thomas | ||
| Exploiting Irregular Memory Parallelism In Quasi-Stencils Through Nonlinear Transformation | Juan Escobedo and Mingjie Lin | ||
| 2:10 | Applications 2 (Roger Moussalli) | FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications | Tianqi Wang, Tong Geng, Xi Jin and Martin Herbordt |
| GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework | Qingqing Xiong, Chen Yang, Rushi Patel, Geng Tong, Anthony Skjellum and Martin Herbordt | ||
| Compressed Sensing MRI Reconstruction on Intel HARPv2 (short) | Yushan Su, Michael Anderson, Jonathan Tamir, Michael Lustig and Kai Li | ||
| Efficient Hardware Acceleration for Design Diversity Calculation to mitigate Common Mode Failures (short) | Maheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran and Benjamin Carrion Schafer | ||
| 3:00 | Afternoon Break and Poster Session 4: Applications | Details | |
| 3:40 | Security and Reliability (Mike Wirthlin) | Fast Voltage Transients on FPGAs: Impact and Mitigation Strategies | Linda L. Shen, Ibrahim Ahmed and Vaughn Betz |
| FASE: FPGA Acceleration of Secure Function Evaluation | Siam Umar Hussain and Farinaz Koushanfar | ||
| 4:25 | Arithmetic (James Davis) | Rethinking Integer Divider Design for FPGA-based Soft Processors | Eric Matthews, Alec Lu, Lesley Shannon and Zhenman Fang |
| High Precision, High Performance FPGA Adders | Martin Langhammer, Bogdan Pasca and Gregg Baeckler | ||
| 5:05 | Close | Closing Session | Ryan Kastner, André DeHon |
| 5:20 | End of Technical Program |
Poster Session 3: Networking and Resource Sharing
| Title | Authors |
|---|---|
| Scalable P4 Deparser for Speeds Over 100Gbps | Pavel Benacek, Jakub Cabal and Juraj Holub |
| Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted Data | Sang-Woo Jun and Arvind |
| Hybrid XML Parser Based on Software and Hardware Co-design | Zhe Pan, Xiaohong Jiang, Jian Wu and Xiang Li |
| Sorting Large Data Sets with FPGA-Accelerated Samplesort | Han Chen, Sergey Madaminov, Michael Ferdman and Peter Milder |
| Cost-effective Energy Monitoring of a Zynq-based Real-time System including dual Gigabit Ethernet | Martin Geier, Dominik Faller, Marian Brändle and Samarjit Chakraborty |
| Improved Techniques for Sensing Intra-Device Side Channel Leakage | William Hunter, Christopher McCarty and Lee Lerner |
| Safe Task Interruption for FPGAs | Sameh Attia and Vaughn Betz |
Poster Session 4: Applications
| Title | Authors |
|---|---|
| OpenCL Kernel Vectorization on the CPU, GPU, and FPGA:A Case Study with Frequent Pattern Compression | Zheming Jin and Hal Finkel |
| A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications | Atsutake Kosuge, Keisuke Yamamoto, Yukinori Akamine, Taizo Yamawaki and Takashi Oshima |
| Monobit Wideband Receiver with Integrated Dithering in FPGA | Dan Pritsker and Colman Cheung |
| An FPGA-based Computing Infrastructure Tailored to Efficiently Scaffold Genome Sequences | Alberto Zeni, Matteo Crespi, Lorenzo Di Tucci and Marco Domenico Santambrogio |
| FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs | Glenn Gihyun Ko, Yuji Chai, Rob A. Rutenbar, David Brooks and Gu-Yeon Wei |
| A Fine-grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model | Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars and H. Peter Hofstee |
| Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms | Murad Qasaimeh, Joseph Zambreno, Phillip Jones, Kristof Denolf, Jack Lo and Kees Vissers |
| Large-scale and High-throughput QR Decomposition on an FPGA | Dajung Lee, Andrei Hagiescu and Dan Pritsker |
| Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints | Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel and Mircea Stan |
Wednesday, May 1
Workshops
Computer Science and Engineering Building
| Time | Workshop Session 1 | Workshop Session 2 | ||
|---|---|---|---|---|
| 8:00 | Security for Custom Computing Machines (Dustin Richmond, University of Washington) | Xilinx ML Suite Developer Tutorial ( Parimal Patel, Xilinx) | ||
| 10:15 | Security for Custom Computing Machines (Continued) | Customizing Implementations with RapidWright in the Domain-specific Age (Chris Lavin, Xilinx) | ||
| 12:15 | Lunch | Lunch | ||
| 1:15 | Edge Intelligence and FCCM: ML + IoT +FCCM (Marilyn Wolf, Georgia Tech) | Intel FPGA New Technology Showcase: Chiplets, High-Bandwidth Memory, and eASIC (David Kehlet, Oliver Tan, and Lawrence Landis, Intel Programmable Solutions Group) | ||
| 5:00 | Closing Remarks | Closing Remarks |
Security for Custom Computing Machines
Date: Wednesday May 1, 2019
Time: 8:00 am – 12:15 pm
Location: CSE 1242
Organizers: Dustin Richmond (UW) and Ryan Kastner (UCSD)
Hardware security is an important design consideration. Recent events have raised awareness of security in general-purpose processors. As experts we must consider: What are equivalent equivalents for custom computing machines? How do we defend against threats that exist today? How do we design our systems to defend against future threats? This is increasingly important as we deploy custom computing machines at unprecedented scales.
Schedule (Preliminary):
| 8:00 | Introduction |
| 8:15 | Matt French/Josh Monson (ISI) |
| 8:30 | Dustin Richmond (University of Washington) Deploying Sensors in the Datacenter |
| 8:45 | David Kohlbrenner (UC Berkeley) A Threat Model for Deploying Secure Hardware Elements on Untrusted FPGAs |
| 9:00 | Jeff Goeders (BYU) Assurance of Trusted 3rd-Party IP for Modern FPGAs |
| 9:15 | Christophe Bobda (University of Florida) System-Level Design of Secure System on Chip |
| 9:30 | Break-Out Session |
| 10:00 | Coffee Break |
| 10:30 | Alric Althoff (Leidos) Quantifying System-Level Side-Channel Vulnerability |
| 10:45 | Aydin Aysu (NC State) Physical Side-Channels Beyond Cryptography: Searching a New Horizon for Hardware Security |
| 11:00 | Nestan Tsiskaridze (UCSB) Quantifying Arbitration Side Channels in FPGAs |
| 11:15 | Ryan Kastner (UCSD) Security Verification for Heterogeneous Systems |
| 11:30 | Jonathan Valamehr (Tortuga Logic) System-Level Security Verification Starts with the Hardware Root of Trust |
| 11:45 | Break-Out Session |
| 12:15 | Lunch |
Xilinx ML Suite Developer Tutorial
Date: Wednesday May 1, 2019
Time: 8:00 am- 10:00 am
Location: CSE 3219
Organizer: Parimal Patel – Xilinx Inc.
With the explosion of large amount of unstructured data generated at various levels, from endpoints to edge to cloud, quick and accurate information processing has driven researchers to consider ways to analyze the data and act on it in real-time. Xilinx’s new Machine Learning Suite enables users to easily evaluate, develop and deploy FPGA-accelerated ML inference using ready-to-run network models so that they can easily integrate machine learning into their research. This tutorial uses the Xilinx ML Suite to deploy models for real-time inference on Amazon EC2 F1 FPGA instances. During this lab you will use Python APIs to accelerate your ML applications with Amazon EC2 F1 instances powered by Xilinx FPGAs. It will provide users an experience on evaluating image classification through Caffe, MxNet and Tensorflow.
Please Note: Attendees will use their laptop to connect to AWS
Customizing Implementations with RapidWright
in the Domain-specific Age
Date: Wednesday May 1, 2019
Time: 10:15 am- 12:15 pm
Location: CSE 3219
Organizer/Speaker: Chris Lavin – Xilinx Inc.
As we enter a new Golden Age of computer architecture, we need new capabilities to build and customize domain-specific applications for FPGAs. RapidWright is an open source framework that provides a gateway to Vivado’s back-end tools enabling fine-grained control over implementation. This workshop provides hands-on experience and live coding with RapidWright to illustrate its capabilities such as:
- Implementation “copy and paste” to create a ~400 instance PicoBlaze overlay
- Using a SAT engine to resolve difficult routing congestion
- Combine a RapidWright-generated SLR bridge with Vivado-based designs
Attendees of this workshop can expect to: (1) gain a deeper understanding of how to leverage Xilinx architecture, (2) know how to use RapidWright and apply its capabilities in their own designs and (3) learn about design methodologies that can lead to near-spec performance.
Please Note: Attendees will use their laptop to connect to AWS
Edge Intelligence and FCCM: ML + IoT +FCCM
Date: Wednesday May 1, 2019
Time: 1:15 pm- 5:00 pm
Location: CSE 1242
Organizer: Marilyn Wolf (Georgia Tech)
This workshop will focus on the emerging intersections between machine learning, IoT, and field-programmable custom computing. Machine learning offers broad applicability to a wide range of applications: manufacturing, agriculture, logistics, health care, smart cities, etc. However, in physically distributed and real-time applications for which IoT architectures are used, machine learning systems cannot be limited to the cloud. The need for low-power, managed-latency, distributed machine learning in turn presents significant opportunities for the application of field-programmable computing. The workshop combines a set of invited talks with contributed presentations.
Intel FPGA New Technology Showcase: Chiplets,
High-Bandwidth Memory, and eASIC
Date: Wednesday May 1, 2019
Time: 1:15- 5:00 pm
Location: CSE 3219
Organizers: David Kehlet, Oliver Tan, and Lawrence Landis
Intel Programmable Solutions Group
Today’s markets are rapidly transforming which is driving massive innovation and putting great demand on capabilities that provide the agility and flexibility to quickly and cost effectively deliver products and solutions. In this workshop, Intel will provide insights into new and unique capabilities that enable engineers, researchers, and innovators to deliver high-performance solutions to drive massive disruption and opportunity.
This workshop include three talks: The first talk is on standardized chiplet interfaces, which are critical for enabling heterogenous compute in package and inter-operability. The second talk is on in-package highbandwidth memory, which is the key to unlocking near-memory computing for emerging applications. The third talk presents a seamless transition from FPGAs to lower power high performance structured ASICs, which opens up new opportunities for the FPGA community.