FCCM
Sunday (May 11, 2014) Workshop on
Domain
Customized Languages (DCLs)
for
Custom Computing Machines
Domain Specific Languages (DSLs) are in common use today to increase
programmer productivity and code quality. DSLs allows application
solutions to be expressed using abstractions that are closer to a problem
domain. DSLs take a wide range of
forms, from markup languages, modeling languages, specification languages,
through tailored programming languages.
Familiar DSLs include HTML, Matlab, SQL, SNORT,
and YACC grammars.
Custom computing machines can offer higher performance and energy
efficiency compared to traditional, general-purpose computing platforms. The
use of field-programmable platforms can avoid the high, fixed manufacturing costs
of ASICs. However, most FCCMs
(Field-Programmable Custom Computing Machines) are still programmed as if they
were ASICs, at the register-transfer level using Verilog or VHDL. This results
in long development times and the need for low-level, hardware-centric design
expertise. These two issues have served as a historical barrier for programmers
and software engineers as they typically do not possess the requisite hardware
design expertise to use these powerful machines. Compounding this problem is the concern
that working at the RTL level can be error prone and result in inefficient and
non-portable designs.
The objective of this workshop is to explore the possibility that domain-customized
languages (DCLs) could provide programmers better access to FCCMÕs, allowing
them to exploit the same benefits of accessibility, productivity, code quality
and design correctness enjoyed by their DSL counterparts. This workshop brings together experts who
will share their experience in creating a diverse set of domain-customized
languages that target FCCMs. Each
expert will first be given 40 minutes to address the following questions:
In short, we ask the experts to tell a compelling story and
illustrate through concrete code examples appropriate for a technical audience
why we should use their specific DCL.
Presentations will then be followed by a 60 minute
open discussion to explore the broader issues of DCL applicability and
acceptability. Specific types of
questions might include:
3:00pm |
Networking Ð Gordon Brebener, Xilinx |
3:40pm |
Graphs ÐEriko Nurvitadhi, Intel |
4:20pm |
Break |
4:30pm |
Model-based FPGA Design Flow Ð Girish Venkataramani, Mathworks |
5:10pm |
Dataflow Ð Rishiyur S. Nikhil, Bluespec |
5:50pm |
Break |
6:00pm |
Discussion |
7:00pm |
FCCM Opening Reception |
Organizers: David Andrews and AndrŽ DeHon