| Wednesday, April 21, 2004 |
| Paper Session 1 : Architecture
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Time-Critical Software Deceleration in an FCCM
P. James-Roxby, G. Brebner, D. Bemmann
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Design Patterns for Reconfigurable Computing
A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier, M. Wrighton
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Virtual Memory Window for Portable Reconfigurable Cryptography Coprocessor
M. Vuletic, L. Pozzi and P. Ienne
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| Poster Session 1 |
| Paper Session 2 : Tools I
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Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs
G. Mittal, D. Zaretsky, X. Tang, P. Banerjee
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PyGen: A MATLAB/Simulink based Tool for Parameterized and Energy
J. Ou and V. Prasanna
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| Paper Session 3 : Arithmetic I
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Automated Least-Significant Bit Datapath Optimization for FPGAs
M.L. Chang and S. Hauck
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An Arithmetic Library and its Application to the N-body Problem
K.H. Tsoi, C.H. Ho, H.C. Yeung and P.H.W. Leong
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Unifying Bit-width Optimisation for Fixed-point and Floating-point Designs
A. Gaffar, O. Mencer, W. Luk and P.Y.K. Cheung
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| Poster Session 2 |
| Paper Session 4 : Communications Applications
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A Dynamically Reconfigurable, Power-Efficient Turbo Decoder
J. Liang, R. Tessier and D. Goeckel
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A Flexible Hardware Encoder for Low-Density Parity-Check Codes
D-U Lee, W. Luk, C. Wang, C. Jones, M. Smith, J. Villasenor
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| Thursday, April 22, 2004 |
| Paper Session 5 : Networking I
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ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
R. Krishnamurthy, S. Yalamanchili, K. Schwan, R. West
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Deep Packet Filter with Dedicated Logic and Read Only Memories
Y. Cho and W. Mangione-Smith
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A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Z. Baker and V. Prasanna
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| Poster Session 3 |
| Paper Session 6 : Applications I
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Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
M. Leeser, S. Miller and H. Yu
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FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method
J. Durbano, F. Ortiz, J. Humphrey, P. Curt, D. Prather
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| Paper Session 7 : Tools II
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Register Binding for FPGAs with Embedded Memory
H. Al Atat and I. Ouaiss
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Defect and Fault Tolerance for Reconfigurable Molecular Computing
M. Tahoori and S. Mitra
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Communications Scheduling for Concurrent Processes on Reconfigurable Computers
M. Gokhale, C. Ahrens, J. Frigo, C. Wolinski
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| Poster Session 4 |
| Paper Session 8 : Applications II
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Reconfigurable Molecular Dynamics Simulator
N. Azizi, I. Kuon, A. Egier, A. Darabiha and P. Chow
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Accelerating Seismic Migration Using FPGA-based Coprocessor Platform
C. He, M. Lu, C. Sun
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| Friday, April 23, 2004 |
| Paper Session 9 : Arithmetic II
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Closing the gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
Keith D. Underwood and K. Scott Hemmert
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FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit
C. Doss and R. Riley
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On-Line IEEE Floating-Point Arithmetic for FPGAs
S. Krueger, P-M. Seidel
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| Poster Session 3 |
| Paper Session 10 : Networking II
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Scalable Multi-Pattern Matching on High-Speed Networks
C. Clark and D. Schimmel
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Pre-decoded CAMs for Efficient and High-Speed NIDS Pattern Matching
Ioannis Sourdis and Dionisios Pnevmatikatos
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