| Wednesday, April 9, 2003 |
| Paper Session 1 : Applications I
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A High I/O Reconfigurable Crossbar Switch
S. Young, P. Alfke, C. Fewer, S. McMillan, B. Blodget, D. Levi
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Congruential sieves on a reconfigurable computer
H.A. Wake and D.A. Buell
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Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm
A. Dollas, C. Kachris, N. Bourbakis
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| Poster Session 1 |
| Paper Session 2 : Network Security
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Implementation of a Content-Scanning Module for an Internet Firewall
J. Moscola, J. Lockwood, R. Loui, M. Pachos
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Compiling Policy Descriptions into Reconfigurable Firewall Processors
T.K. Lee, S. Yusuf, W. Luk, M. Sloman, E. Lupu and N. Dulay
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| Paper Session 3 : Communication Techniques
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Compact FPGA-based True and Pseudo Random Number Generators
K.H. Tsoi, K.H. Leung, P.H.W. Leong
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Accelerating Bit Error Rate Testing Using a System Level Design Tool
V. Singh, A. Root, E. Hemphill, N. Shirazi and J. Hwang
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A Hardware Gaussian Noise Generator for Channel Code Evaluation
D-U. Lee, W. Luk, J. Villasenor, P.Y.K. Cheung
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| Poster Session 2 |
| Paper Session 4 : Arithmetic I
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Perturbation Analysis for Word-length Optimization
G. Constantinides
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Improved Small Multiplier Based Multiplication, Squaring and Division
B.R. Lee and N. Burgess
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| Thursday, April 10, 2003 |
| Paper Session 5 : Device Architecture
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Efficient Application Representation for HASTE: Hybrid Architectures with a Single Executable
B. Levine, H. Schmit
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Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
K. Eguro, S. Hauck
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Asynchronous PipeRench: Architecture and Performance Estimations
H. Kagotani, H. Schmit
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| Poster Session 3 |
| Paper Session 6 : Fault Modeling and Recovery
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The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
M. Wirthlin, D. Johnson, N. Rollins, M. Caffrey, P. Graham
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Adaptive Fault Recovery for Networked Reconfigurable Systems
W. Xu, R. Ramanarayanan, R. Tessier
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| Paper Session 7 : Applications II
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Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware
J. Frigo, D. Palmer, M. Gokhale and M. Popkin-Paine
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Design and Implementation of a Generic 2-D orthogonal Discrete Wavelet Transform on FPGA
A. Benkrid, K. Benkrid, D. Crookes
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Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines
H. Quinn
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| Poster Session 4 |
| Paper Session 8 : Arithmetic II
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Floating Point Unit Generation and Evaluation for FPGAs
J. Liang, R. Tessier, O. Mencer
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Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs
X. Wang, B. Nelson
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| Friday, April 11, 2003 |
| Paper Session 9 : Compilation Techniques
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Data Search and Reorganization using FPGAs: Application to Spatial Pointer-based Data Structures
P. Diniz and J. Park
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Simulation and Synthesis of CSP-based Interprocess Communication
P. Jackson, B. Hutchings
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Source Level Debugger for the Sea Cucumber Synthesizing Compiler
K.S. Hemmert, J. Tripp, B. Hutchings
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| Poster Session 3 |
| Paper Session 10 : Programming Frameworks
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Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications
J. Ou, S. Choi, V. Prasanna
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Reconfigurable Computing Application Frameworks
A. Slade, B. Nelson, B. Hutchings
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