FCCM 2025 Program (Preliminary)
*All times shown in the EST (UTC-5)
Sunday (May 4) and Wednesday (May 7): Workshops and Tutorials
Sunday – May 4
| 12:00 pm – 5:00 pm | Registration Open |
| 1 pm โ 4:30 pm |
Tutorials and Workshops |
| 6:00 pm – 7:15 pm |
Sunday’s Panel Sunday Panel Discussion: The Future of FCCMs Beyond Mooreโs Law |
Monday – May 5
โ indicates best paper candidate
Dataset Available
Dataset Reviewed 
Dataset Reproducible 
| 7:30 am – 9:00 am | Registration |
| 9:00am – 9:20 am | Welcoming Remarks |
| 9:20 am – 10:30 am |
Session 1 – Abstractions, Programming Models, and Tools 1 Chair: TBD |
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AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs Dilshan Sampath Kumarathunga Then Kuttiyage (Simon Fraser University); Qilin Hu (Hunan University); Zhenman Fang (Simon Fraser University) |
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RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs Jiho Kim, Cong (Callie) Hao (Georgia Institute of Technology) |
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HP-FFT: A General High-Performance FFT Generator Using High-Level Synthesis (short paper) Chengyue Wang, Jiahao Zhang (UCLA); Yingquan Wu (Tenafe, Inc.); Jason Cong (UCLA) |
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FREEDOM: FPGA-based Hardware Redaction Emulator (short paper) Benjamin Carrion Schaefer, Chaitali Gajanan Sathe, Yiorgos Makris (The University of Texas at Dallas) |
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Poster Introductions |
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| 10:30 am – 11:30 am | Poster Session 1 |
| 11:30 am – 12:30 pm |
Session 2 – Memories Chair: TBD |
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HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance Yang Yang, Kyle Tseng, Viktor Prasanna (University of Southern California); Rajgopal Kannan (DEVCOM Army Research Lab) |
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High Throughput Matrix Transposition on HBM-Enabled FPGAs Canberk Sonmez, Mohamed Shahawy, Paolo Ienne (EPFL) |
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Banked Memories for Soft SIMT Processors Martin langhammer (Altera, Imperial College London); George A. Constantinides (Imperial College London, UK) |
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| 12:30 pm – 2:00 pm | Lunch |
| 2:00 pm – 3:00 pm |
Session 3 -Applications I Chair: TBD |
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Soaring with ICARUS: an HW/SW Heterogeneous Accelerator for Multi-Modal Image Registration Giuseppe Sorrentino, Paolo Salvatore Galfano (Politecnico di Milano); Eleonora D’Arnese (University of Edinburgh); Davide Conficconi (Politecnico di Milano) |
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HighWave: Large-scale High-Bandwidth Wave Simulations on FPGAs Dimitrios Gourounas, Austin G. James, Bagus Hanindhito (The University of Texas at Austin); Arash Fathi (ExxonMobil); Lizy K. John, Andreas Gerstlauer (The University of Texas at Austin) |
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SMART: High-Performance SAR ATR through Model-Architecture Co-Design on FPGA Sachini Wickramasinghe, Yi-Chien Lin, Cauligi Raghavendra, Viktor Prasanna (University of Southern California) |
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| 3:00 pm – 3:15 pm | Break |
| 3:15 pm – 4:05 pm |
Session 4 -Abstractions, Programming Models, and Tools 2 Chair: TBD |
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Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface Erika Hunhoff (University of Colorado, Boulder), Joseph Melber (AMD), Kristof Denolf (AMD), Andra Bisca (AMD), Samuel Bayliss (AMD), Stephen Neuendorffer (AMD), Jeff Fifield (AMD), Jack Lo (AMD), Pranathi Vasireddy (AMD), Phil James-Roxby (AMD), Eric Keller (University of Colorado, Boulder) |
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Efficient and Distributed Computation of Electron Repulsion Integrals on AI Engines Johannes Menzel, Christian Plessl (Paderborn University) |
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Chronbench: An Incremental HDL Benchmark Suite Zakary Nafziger, Steve Wilton (University of British Columbia) |
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| 4:00 pm – 6:30 pm | Prep for Demo Night, Crystal Bridges Excursion |
| 6:30 pm – 9:00 pm | Demo Night, and Ph.D. Forum |
Tuesday – May 6
| 7:30 am – 8:45 am | Registration Open |
| 8:45 am – 9:00 am | Announcements |
| 9:00 am – 10:10 am |
Session 5 – Abstractions, Programming Models, and Tools 3 Chair: TBD |
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ITERA-LLM: Boosting Sub-8-Bit Large Language Model Inference Through Iterative Tensor Decomposition Yinting Huang, Keran Zheng, Zhewen Yu, Christos-Savvas Bouganis (Imperial College London) |
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InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Zifan He, Anderson Truong (University of California, Los Angeles); Yingqi Cao (University of California, San Diego); Jason Cong (University of California, Los Angeles) |
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LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation (short paper) Zixi Zhang (University of Cambridge); Balint Szekely, Pedro Gimenes (Imperial College London); Greg Chadwick, Hugo McNally (lowRISC); Jianyi Cheng (University of Edinburgh); Robert Mullins (University of Cambridge); Yiren Zhao (Imperial College London) |
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SoftCUDA: Running CUDA on Softcore GPU (short paper) Chihyo Ahn, Ruobing Han, Udit Subramanya, Jisheng Zhao (Georgia Institute of Technology); Blaise Tine (University of California, Los Angeles); Hyesoon Kim (Georgia Tech) |
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| Poster Introductions | |
| 10:10am – 11:10am | Poster Session 2 |
| 11:10am – 12:30 pm |
Session 6 – CAD/NOC Chair: TBD |
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Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox Shashwat Shrivastava (EPFL); Stefan Nikoliฤ (University of Novi Sad); Sun Tanaka (EPFL); Chirag Ravishankar, Dinesh Gaitonde (AMD); Mirjana Stojilovic (EPFL) |
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N-TORC: Native Tensor Optimizer for Real-time Constraints Suyash Vardhan Singh, Iftakhar Ahmad (University of South Carolina); Miaoqing Huang, David Andrews (University of Arkansas); Austin Downey, Jason D. Bakos (University of South Carolina) |
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NoH: NoC Compilation in High Level Synthesis Jake Ke, Sihao Liu (UCLA); Licheng Guo (RapidStream Design Automation, Inc.); Zifan He, Suhail Basalama (University of California, Los Angeles); Linghao Song (Yale University); Yuze Chi (RapidStream Design Automation, Inc.); Jason Cong, Tony Nowatzki (UCLA) |
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A partitioning-based CAD flow for interposer-based multi-die FPGAs Mahesh A. Iyer (Altera); Andrew Kahng (University of California San Diego); Jason Luu (Intel); Bodhisatta Pramanik (University of California San Diego); Kristofer Vorwerk, Grace Zgheib (Altera) |
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| 12:30 pm – 2:00 pm | Lunch |
| 2:00 pm – 3:10 pm |
Session 7 – Applications 2 -Embedded and IoT Edge Chair: TBD |
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Transfer Learning on the Edge for a Wireless Application Using an SoC Platform Yiyue Jiang (Northeastern University); John Dooley, Aidan Edward Colgan (Maynooth University); Zhilin Ren (Northeastern University); Jonathan Guimaraes Ribeiro (Maynooth University); Miriam Leeser (Northeastern University) |
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Moyogi: A Memory-centric Accelerator for Low-Latency Random Forest Inference on Embedded Devices Alessandro Verosimile, Francesco Peverelli, Marco D. Santambrogio (Politecnico di Milano) |
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IceSpy: Reconfigurable Edge Accelerator for Scalable and Private Structural Health Monitoring Alexandra Zhang Jiang, Jonathan Ta, Yuqiao Li, Zhou Li, Nalini Venkatasubramanian (University of California, Irvine); Monica D. Kohler (California Institute of Technology); Sang-Woo Jun (University of California Irvine) |
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| Poster Introductions | |
| 3:10 pm – 4:10 pm | Poster Session 3 |
| 4:10 pm – 5:10 pm |
Session 8 – ML Architectures |
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NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference Marta Andronic, George A. Constantinides (Imperial College London, UK) |
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An Efficient FPGA-based Hardware Accelerator of Fully Quantized Mamba-2 Kailing Zhou, Han Jiao, Wenjin Huang, Yihua Huang (Sun Yat-sen University) |
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FPGA-based Approximate Multiplier for FP8 Ruiqi Chen, Yangxintong Lyu, Han Bao (Vrije Universiteit Brussel); Jiayu Liu (University College London); Yanxiang Zhu (VeriMake Innovation Lab); Shidi Tang, Ming Ling (Southeast University); Bruno da Silva (Vrije Universiteit Brussel) |
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| 5:00 pm – 5:30 pm | Best Paper Award and Closing Ceremony |
Wednesday – May 7
| 9:00 AM to 12:00 PM | Tutorials and Workshops |
| 12:00 PM to 5:00 PM | Tutorials and Workshops |