SCHEDULE

Sunday, May 2nd

2:00pm Registration opens

2:00pm Altera Workshop

3:00pm Xilinx Workshop

4:00pm Floating-Point Benchmarks Discussion

5:00pm Wine and Cheese Reception

Monday, May 3rd

  8:15am Opening Remarks

  8:30am Session 1: Computer Vision and Graphics Processing

  9:55am Poster Session 1

10:45am Session 2: Run-Time Systems

12:20pm Lunch

  1:45pm Session 3: Supercomputing

  3:15pm Poster Session 2 (Day 1 Short Papers)

  4:15pm Session 4: Open-Source Tools and Platforms

  6:00pm Demo Night and Reception

Tuesday, May 4th

  8:30am Admin Updates

  8:45am Session 5: Application Development and CAD Tools

10:20am Poster Session 3

11:00am Session 6: Machine Learning and String Matching

12:25pm Lunch

  1:45pm Session 7: Systems and Architectures

  3:15pm Poster Session 4 (Day 2 Short Papers)

  4:15pm Session 8: Encryption

  5:05pm Closing Remarks

PROGRAM

MONDAY

Session 1

Computer Vision and Graphics Processing
Chair: David Andrews
Monday 8:30am

Fast and Efficient FPGA-based Feature Detection employing the SURF algorithm

Bouris Dimitris,  Nikitakis Antonis,  Papaefstathiou Ioannis
Technical University of Crete

Accelerating Viola-Jones Face Detection to FPGA-Level using GPUs

Daniel Hefenbrock,  Jason Oberg,  Nhat Tan Nguyen Thanh,  Ryan Kastner,  Scott Baden
CSE at UCSD

Accelerating the Nonuniform Fast Fourier Transform using FPGAs

Srinidhi Kestur,  Sungho Park,  Kevin Irick,  Vijaykrishnan Narayanan
Dept of Computer Science and Engineering Pennsylvania State University

Increased Performace of FPGA-Based Color Classification System

Junguk Cho,  Bridget Benson,  Sunsern Cheamanukul,  Ryan Kastner
University of California San Diego

A Pipelined Hardware Architecture for High-speed Optical Flow Estimation using FPGA

Seunghun Jin,  Dongkyun Kim,  Duc Dung Nguyen,  Jae Wook Jeon
Sungkyunkwan University

Session 2

Run-Time Systems
Chair: Lesley Shannon
Monday 10:45am

Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive

Jason Agron and David Andrews
University of Arkansas

Improving the Robustness of a Softcore Processor against SEUs by using TMR and Partial Reconfiguration

Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Kumamoto University

Energy-aware Optimisation for Run-Time Reconfiguration

Tobias Becker,  Wayne Luk,  Peter Y. K. Cheung
Imperial College London

A Communication Aware Online Task Scheduling Algorithm for the FPGA-based Partially Reconfigurable Systems

Yi Lu,  Thomas Marconi,  Koen Bertels,  Georgi Gaydadjiev
TU Delft
will be presented during poster session 1

Fine-grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Dirk Koch1,  Christian Beckhoff 2,  Jim Torrison1
1 University of Oslo Norway   2 ReCoBus

Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-based FPGAs

Anargyros Ilias,  Kyprianos Papadimitriou,  Apostolos Dollas
Technical University of Crete

Design of a Reconfigurable Hybrid Database System

Bernd Scheuermann
SAP Research SAP AG

Session 3

Supercomputing
Chair: Duncan Buell
Monday 1:45pm

Hardware Acceleration of Approximate Tandem Repeat Detection

Tomas Martinek1 and Matej Lexa2
1 Brno University of Technology   2 Masaryk University

Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence

Arpith Jacob,  Jeremy Buhler,  Roger Chamberlain
Washington University in St. Louis

Reaping the processing potential of FPGA on double-precision floating-point operations: an eigenvalue solver case study

Miaoqing Huang1 and Ozlem Kilic2
1 University of Arkansas    2 The Catholic University of America

Short Papers

Performing Floating-Point Accumulation on a modern FPGA in Single and Double Precision

Tarek Ould Bachir and Jean-Pierre David
Ecole Polytechnique de Montreal

Blocking LU decomposition for FPGAs

Guiming Wu1,  Yong Dou1,  Gregory Peterson2
1 National Laboratory for Parallel and Distributed Processing National University of Defense Technology China      2 Electrical Engineering and Computer Science University of Tennessee

Acceleration of a DWT-based Algorithm for Short Exposure Stellar Images Processing on a HPRC Platform

Javier Garrigós,  J. Javier Martínez,  Isidro Villó,  Javier Toledo,  J. Manuel Ferrández
Universidad Politécnica de Cartagena

Session 4

Open-Source Tools and Platforms
Chair: Gordon Brebner
Monday 4:15pm

A Bespoke Time-Triggered Switch for Hard Real-Time Communication Using Ethernet Nodes

Gonzalo Carvajal1 and Sebastian Fischmeister2
1 Universidad de Concepcion    2 University of Waterloo

Designing Modular Hardware Accelerators in C with ROCCC 2.0

Jason Villarreal1,  Adrian Park1,  Walid Najjar2,  Robert Halstead2
1 Jacquard Computing Inc.    2 University of California Riverside

SIRC: An Extensible Reconfigurable Computing Communication API

Ken Eguro
Microsoft Research

TUESDAY

Session 5

Application Development and CAD Tools
Chair: Miriam Leeser
Tuesday 8:45am

ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs

Christopher Neely1,  Gordon Brebner1,  Weijia Shang2
1 Xilinx Inc.    2 Santa Clara University

Odin II - An Open-source Verilog HDL Synthesis Tool for Academic CAD Flows

Peter Jamieson1,  Kenneth Kent2,  Farnaz Gharibian3,  Lesley Shannon3
1 Miami University    2 University of New Brunswick    3 Simon Fraser University

Automated Precision Analysis: A Polynomial Algebraic Approach

David Boland and George Constantinides
Imperial College London

Short Papers

FPGA Circuit Synthesis of Accelerator Data-Parallel Programs

Satnam Singh,  Barry Bond,  Lubomir Litchev,  Kerry Hammil
Microsoft

Impulse C vs. VHDL for Accelerating Tomographic Reconstruction

Jimmy Xu1,  Nikhil Subramanian2,  Scott Hauck1,  Adam Alessio3
1 University of Washington EE    2 University of Washington EE / Microsoft
3 University of Washington Department of Radiology

Integrating High-Level Synthesis into MPI

Andrew W. H. House1,  Manuel Saldana2,  Paul Chow1
1 University of Toronto    2 Arches Computing Systems

Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems

Joon Edward Sim1,  Weng-Fai Wong1,  Gregor Walla2,  Tobias Ziermann2,  Jürgen Teich2
1 National University of Singapore Singapore    2 University of Erlangen-Nuremberg Germany

Session 6

Machine Learning, String Matching, and Networking
Chair: Shep Siegel
Tuesday 11:00am

BURAQ: A Dynamically Reconfigurable System for Stateful Measurement of Network Traffic

Faisal Khan,  Nicholas Hosein,  Scott Vernon,  Soheil Ghiasi
University of California Davis

A Memory-Efficient and Modular Approach for String Matching on FPGAs

Hoang Le and Viktor Prasanna
USC

A Large-scale Architecture for Restricted Boltzmann Machines

Sang Kyun Kim,  Peter McMahon,  Kunle Olukotun
Stanford University

Short Papers

A Heterogeneous FPGA Architecture for Support Vector Machine Training

Markos Papadonikolakis and Christos-Savvas Bouganis
Imperial College

A High-Speed and Memory Efficient Pipeline Architecture for Packet Classification

Yeim-Kuan Chang,  Yi-Shang Lin,  Cheng-Chien Su
Department of Computer Science and Information Engineering National Cheng Kung University

Session 7

Systems and Architectures
Chair: Paul Chow
Tuesday 1:45pm

FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures

Tayo Oguntebi,  Sungpack Hong,  Jared Casper,  Nathan Bronson,  Christos Kozyrakis,  Kunle Olukotun
Stanford University

Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance

Hadi Parandeh-Afshar and Paolo Ienne
EPFL (Ecole Polytechnique Federale de Lausanne)

Using the Power Side Channel of FPGAs for Communication

Daniel Ziener,  Florian Baueregger,  Jürgen Teich
University of Erlangen-Nuremberg

Short Papers

A Comparative Study on the Architecture Templates for Dynamic Nested Loops

Jason Cong and Yi Zou
UCLA

Customizable composition and parametrization of design optimizations

Qiang Liu,  Tim Todman,  Wayne Luk,  George A. Constantinides
Imperial College London

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip

Diana Goehringer1,  Michael Huebner2,  Michael Benz1,  Juergen Becker2
1 Fraunhofer IOSB    2 Karlsruhe Institute of Technology (KIT)

Session 8

Encryption
Chair: Andre DeHon
Tuesday 4:15pm

Enumeration of Bent Boolean Functions by Reconfigurable Computer

Jennifer Shafer1,  Stuart Schneider2,  Jon Butler2,  Pantelimon Stanica2
1 US Naval Academy    2 Naval Postgraduate School

DPA Resistant AES on FPGA using Partial DDL

Jens-Peter Kaps and Rajesh Velegalati
George Mason University

POSTER SESSIONS

POSTER SESSION 1
Chair: Mark L. Chang
Monday 9:55am

Redsharc: An Abstract Stream Programming Model for FPGAs

William Kritikos1, Andrew Schmidt1, Ron Sass1, Erik Anderson2, Michel Sika2, Matthew French2
1 University of North Carolina at Charlotte
2 Information Sciences Institute - University of Southern California

An FPGA Architecture for Accelerating Graphics Processing and General Purpose Computations

Marcus Dutton and David Keezer
Georgia Institute of Technology

Using Variable Precision Floating Point with Embedded Hard and Soft Core Processors

Jainik Kathiara1, Miriam Leeser1, Paolo Palana2
1 Northeastern University
2 University of Rome

Accelerator performance comparison for mixed precision linear solvers

JunKyu Lee1, Junqing Sun2, Gregory Peterson1, Robert Harrison3, Robert Hinde3
1 Department of Electrical Engineering and Computer Science University of Tennessee
Knoxville Tennessee USA
2 Marvell Semiconductor Inc. Santa Clara California USA
3 Department of Chemistry University of Tennessee Knoxville Tennessee USA

An Open-Source PR Toolkit for Xilinx FPGAs

Ali Sohanghpurwala, Peter Athanas, Aaron Wood
VT

openHCA: An Open Source Framework to Simplify FPGA Implementation of Streaming Applications

Christopher Wolfe and Cameron Patterson
Virginia Tech

FT-DyMPSoC: Analytical Model for Fault-Tolerant Dynamic MPSoC

Hung-Manh Pham, Sebastien Pillement, Didier Demigny
CAIRN/IRISA

POSTER SESSION 2: Day 1 Short Papers
Chair: Ken Eguro
Monday 3:15pm

POSTER SESSION 3
Chair: Matt French
Tuesday 10:20am

Framework Improvement for Multi-module Embedded Reconfigurable Systems

Muhammad Hasan1, Timothy Davis1, Kensinger Troy Kensinger1, Sotirios Ziavras2
[1] Texas A & M University
[2] New Jersey Institute of Technology

Analysis and Architecture Design of Scalable Fraction Motion Estimation for H.264 Encoding

Jasmina Vasiljevic and Andy Ye
Ryerson University

Restructuring GNU Radio for Agile Radio Design

Charles Irick and Peter Athanas
Virginia Tech

ATHENa – Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs

Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol
George Mason University

An Open-Source, Fast, Cost-Efficient Hardware/Software Partitioning Tool

Iakovos Mavroidis1, Ioannis Papaefstathiou1, Alessandro Garbo2, Sergio Nocco2, Jun-Kyoung Kim2, Gianpiero Cabodi2, Luciano Lavagno2
1 Microprocessor and Hardware Lab Technical University of Crete
2 Politecnico di Torino

From Tree to Forest: A Parallel Architecture for Flexible Flow Matching on FPGA

Weirong Jiang and Viktor Prasanna
University of Southern California

Parallel data sort using networked FPGAs

Janardhan Singaraju and John Chandy
University of Connecticut

POSTER SESSION 4: Day 2 Short Papers
Chair: Jason Bakos
Tuesday 3:15pm