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FCCM 2002

The 10th IEEE International Symposium on
Field-Programmable Custom Computing Machines

April 21-24, 2002

Technical Programme : Papers

Monday, April 22, 2002
Paper Session 1 : Applications I
Image Registration of real-time video data using the SONIC reconfigurable computer platform
Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk, Jason Pelly
A Massively Parallel RC4 Encryption Engine
K.H. Tsoi, K.H. Lee and P.H.W. Leong
An FPGA Implementation of Triangle Mesh Decompression
T. Mitra, T. Chiush
Poster Session 1
Paper Session 2 : Networking I
Single-chip Gigabit Mixed-version IP Router on Virtex-II Pro
G. Brebner
Control and Configuration Software for a Reconfigurable Networking Hardware Platform
T. Sproull, J. Lockwood, D. Taylor
Paper Session 3 : Tools I
Peer-to-peer Hardware-software Interfaces for Reconfigurable Fabrics
M. Mishra and S. Goldstein
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
O. Mencer
Coarse-Grain Pipelining for Multiple FPGA Architectures
Heidi Ziegler, Mary Hall, Joonseok Park, Pedro Diniz and Byoungro So
Poster Session 2
Paper Session 4 : Template Matching
FPGA-based Template Matching using Distance Transforms
S. Hezel, A. Kugel, R. Manner and D. Gavrila
Reconfigurable Shape-Adaptive Template Matching Architectures
J. Gause, P.Y.K. Cheung, W. Luk
Tuesday, April 23, 2002
Paper Session 5 : Networking II
Assisting Network Intrusion Detection with Reconfigurable Hardware
R. Franklin, D. Carver and B. Hutchings
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing
P. Bellos, J. Flidr, T. Lehman, B. Schott and K. Underwood
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic
G. Memik, S. Memik and W. Mangione-Smith
Poster Session 3
Paper Session 6 : Architecture I
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
G. Stitt, B. Grattan and F. Vahid
Queue Machines: Hardware Compilation in Hardware
H. Schmit, B. Levine and B. Ylvisaker
Paper Session 7 : Applications II
Custom Computing Machines for the Set Covering Problem
C. Plessl and M. Platzner
Using Floating Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations
G. Lienhart, A. Kugel and R. Manner
Analysis and Implementation of the Discrete Element Method using a Dedicated Highly Parallel Architecture in Reconfigurable Computing
B.C. Schaffer, S.F. Quigley and A.H.C. Chan
Poster Session 4
Paper Session 8 : Architecture II
Mobile Memory: Improving memory locality in very large reconfigurable fabrics
Rong Yan and Seth Goldstein
Hardware-Assisted Fast Routing
A. DeHon, R. Huang, J. Wawrzynek
Wednesday, April 23, 2002
Paper Session 9 : Tools II
Optimum Wordlength Allocation
G. Constantinides, P.Y.K. Cheung, W. Luk
Precis: A Design-Time Precision Analysis Tool
M. Chang and S. Hauck
Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems
D. Kulkami, W. Najjar, R. Rinker and F. Kurdahi
Poster Session 3
Paper Session 10 : Image Compression
Hyperspectral Image Compression on Reconfigurable Platforms
T. Fry, S. Hauck
MPEG-compliant Entropy Decoding on FPGA-augmented TriMedia/CPU64
M. Sima, S. Cotofina, S. Vassiliadis, J. van Eijndhoven, K. Vissers